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OMAP3503ECBB

Texas Instruments Embedded Controllers & Processors
  • 参考价格：￥209.97-￥222.59

更新日期：2024-04-01 00:04:00

OMAP3503ECBB

Texas Instruments Embedded Controllers & Processors

产品简介：Sitara 处理器: Arm Cortex-A8、LPDDR

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  • 参考价格：￥209.97-￥222.59

OMAP3503ECBB 供应商

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  • 型号
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OMAP3503ECBB 中文资料属性参数

  • 制造商：Texas Instruments
  • 产品种类：处理器 - 专门应用
  • 类型：Applications Processor
  • 工作电源电压：- 0.5 V to + 1.6 V
  • 最大工作温度：+ 70 C
  • 安装风格：SMD/SMT
  • 封装 / 箱体：FCBGA-515
  • 核心：ARM Cortex A8
  • 数据总线宽度：32 bit
  • 接口类型：I2C, SPI, UART, USB
  • 最大时钟频率：720 MHz
  • 工作温度范围：0 C to + 70 C
  • 处理器系列：OMAP3503
  • 程序存储器大小：64 KB
  • 程序存储器类型：112 KB
  • 工厂包装数量：168

产品特性

  • OMAP3 Devices: OMAP™ 3 Architecture MPU Subsystem Up to 720-MHz ARM® Cortex™-A8 Core NEON™ SIMD Coprocessor PowerVR® SGX™ Graphics Accelerator Tile-Based Architecture Delivering up to 1 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine-Grained Task Switching, Load Balancing, and Power Management Programmable High-Quality Image Anti-Aliasing Fully Software-Compatible with ARM9™ Commercial and Extended Temperature Grades
  • OMAP™ 3 Architecture
  • MPU Subsystem Up to 720-MHz ARM® Cortex™-A8 Core NEON™ SIMD Coprocessor
  • Up to 720-MHz ARM® Cortex™-A8 Core
  • NEON™ SIMD Coprocessor
  • PowerVR® SGX™ Graphics Accelerator Tile-Based Architecture Delivering up to 1 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine-Grained Task Switching, Load Balancing, and Power Management Programmable High-Quality Image Anti-Aliasing
  • Tile-Based Architecture Delivering up to 1 MPoly/sec
  • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  • Fine-Grained Task Switching, Load Balancing, and Power Management
  • Programmable High-Quality Image Anti-Aliasing
  • Fully Software-Compatible with ARM9™
  • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core ARMv7 Architecture TrustZone® Thumb®-2 MMU Enhancements In-Order, Dual-Issue, Superscalar Microprocessor Core NEON Multimedia Architecture Over 2x Performance of ARMv6 SIMD Supports Both Integer and Floating-Point SIMD Jazelle® RCT Execution Environment Architecture Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARMv7 Architecture TrustZone® Thumb®-2 MMU Enhancements
  • TrustZone®
  • Thumb®-2
  • MMU Enhancements
  • In-Order, Dual-Issue, Superscalar Microprocessor Core
  • NEON Multimedia Architecture
  • Over 2x Performance of ARMv6 SIMD
  • Supports Both Integer and Floating-Point SIMD
  • Jazelle® RCT Execution Environment Architecture
  • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
  • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture: -KB Instruction Cache (4-Way Set-Associative) -KB Data Cache (4-Way Set-Associative) -KB L2 Cache
  • -KB Instruction Cache (4-Way Set-Associative)
  • -KB Data Cache (4-Way Set-Associative)
  • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess: ARM Instructions – Little Endian ARM Data – Configurable
  • ARM Instructions – Little Endian
  • ARM Data – Configurable
  • External Memory Interfaces: General Purpose Memory Controller (GPMC) 16-Bit-Wide Multiplexed Address and Data Bus Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth) Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • General Purpose Memory Controller (GPMC) 16-Bit-Wide Multiplexed Address and Data Bus Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth) Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • 16-Bit-Wide Multiplexed Address and Data Bus
  • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP) CCD and CMOS Imager Interface Memory Data Input BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface Glueless Interface to Common Video Decoders Resize Engine Resize Images From 1/4x to 4x Separate Horizontal and Vertical Control
  • CCD and CMOS Imager Interface
  • Memory Data Input
  • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
  • Glueless Interface to Common Video Decoders
  • Resize Engine Resize Images From 1/4x to 4x Separate Horizontal and Vertical Control
  • Resize Images From 1/4x to 4x
  • Separate Horizontal and Vertical Control
  • Display Subsystem Parallel Digital Output Up to 24-Bit RGB HD Maximum Resolution Supports Up to 2 LCD Panels Support for Remote Frame Buffer Interface (RFBI) LCD Panels 2 10-Bit Digital-to-Analog Converters (DACs) Supporting: Composite NTSC and PAL Video Luma and Chroma Separate Video (S-Video) Rotation 90-, 180-, and 270-Degrees Resize Images From 1/4x to 8x Color Space Converter 8-Bit Alpha Blending
  • Parallel Digital Output Up to 24-Bit RGB HD Maximum Resolution Supports Up to 2 LCD Panels Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  • Up to 24-Bit RGB
  • HD Maximum Resolution
  • Supports Up to 2 LCD Panels
  • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting: Composite NTSC and PAL Video Luma and Chroma Separate Video (S-Video)
  • Composite NTSC and PAL Video
  • Luma and Chroma Separate Video (S-Video)
  • Rotation 90-, 180-, and 270-Degrees
  • Resize Images From 1/4x to 8x
  • Color Space Converter
  • 8-Bit Alpha Blending
  • Serial Communication 5 Multichannel Buffered Serial Ports (McBSPs) 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5) 5-KB Transmit and Receive Buffer (McBSP2) SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations Direct Interface to I2S and PCM Device and TDM Buses 128-Channel Transmit and Receive Mode Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface) High-, Full-, and Low-Speed Multiport USB Host Subsystem 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface One HDQ™/1-Wire® Interface UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • 5 Multichannel Buffered Serial Ports (McBSPs) 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5) 5-KB Transmit and Receive Buffer (McBSP2) SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations Direct Interface to I2S and PCM Device and TDM Buses 128-Channel Transmit and Receive Mode
  • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  • 5-KB Transmit and Receive Buffer (McBSP2)
  • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  • Direct Interface to I2S and PCM Device and TDM Buses
  • 128-Channel Transmit and Receive Mode
  • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
  • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
  • High-, Full-, and Low-Speed Multiport USB Host Subsystem 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
  • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
  • One HDQ™/1-Wire® Interface
  • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
  • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces: Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management SmartReflex™ Technology Dynamic Voltage and Frequency Scaling (DVFS)
  • SmartReflex™ Technology
  • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces IEEE 1149.1 (JTAG) Boundary-Scan Compatible ETM Interface Serial Data Transport Interface (SDTI)
  • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
  • ETM Interface
  • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only), Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

产品概述

devices are based on the enhanced OMAP 3 architecture.The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:The device supports high-level operating systems (HLOSs), such as:This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.The following subsystems are part of the device:The device also offers:OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:
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OMAP3503ECBB 数据手册

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