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A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications

A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications

Meng Fu (University of Melbourne, Melbourne, Australia), Stan Skafidas (University of Melbourne, Melbourne, Australia), and Iven Mareels (University of Melbourne, Melbourne, Australia)
Copyright: © 2018 |Volume: 10 |Issue: 3 |Pages: 12
ISSN: 1941-8663|EISSN: 1941-8671|EISBN13: 9781522543961|DOI: 10.4018/IJITN.2018070103
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MLA

Fu, Meng, et al. "A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications." IJITN vol.10, no.3 2018: pp.21-32. https://doi.org/10.4018/IJITN.2018070103

APA

Fu, M., Skafidas, S., & Mareels, I. (2018). A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications. International Journal of Interdisciplinary Telecommunications and Networking (IJITN), 10(3), 21-32. https://doi.org/10.4018/IJITN.2018070103

Chicago

Fu, Meng, Stan Skafidas, and Iven Mareels. "A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications," International Journal of Interdisciplinary Telecommunications and Networking (IJITN) 10, no.3: 21-32. https://doi.org/10.4018/IJITN.2018070103

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Abstract

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.

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