This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11 μm standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7 dBm and a drain efficiency of over 38% from 1.6 GHz to 2.2 GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5 dBm and 33% (@ACLR =-33 dBc).