A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
IEICE Transactions on Communications
Online ISSN : 1745-1345
Print ISSN : 0916-8516
Regular Section
A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
Seongyong AHN, Hyejeong HONG, HyunJin KIM, Jin-Ho AHN, Dongmyong BAEK, Sungho KANG
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Keywords: network intrusion detection system, deep packet inspection, pattern matching, brute-force algorithm
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2010 Volume E93.B Issue 9 Pages 2440-2442

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Abstract

This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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