High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipo&#x03BB;aos Switch Architecture [Invited]

N. Terzenidis; M. Moralis-Pegios; G. Mourgias-Alexandris; T. Alexoudi; K. Vyrsokinos; N. Pleros

doi:10.1364/JOCN.10.00B102

Journal of Optical Communications and Networking
Vol. 10,
Issue 7,
pp. B102-B116
(2018)
•https://doi.org/10.1364/JOCN.10.00B102

High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited]

N. Terzenidis, M. Moralis-Pegios, G. Mourgias-Alexandris, T. Alexoudi, K. Vyrsokinos, and N. Pleros

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N. Terzenidis, M. Moralis-Pegios, G. Mourgias-Alexandris, T. Alexoudi, K. Vyrsokinos, and N. Pleros, "High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited]," J. Opt. Commun. Netw. 10, B102-B116 (2018)

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Abstract

The emergence of disaggregation in data center (DC) architectures as a way to increase resource utilization introduces significant challenges to the DC switching infrastructure, which has to ensure high bandwidth and low-latency communication along with high-radix connectivity. This paper examines the network requirements in disaggregated systems and reviews the credentials of state-of-the-art high-radix optical switch architectures. We also demonstrate a novel optical packet switch design, called $Hipo λ aos$ , that satisfies these requirements by combining N-port broadcast-and-select and $N \times N$ arrayed waveguide grating router-based forwarding schemes in $N^{2}$ -port connectivity configurations. The $Hipo λ aos$ switch provides sub-μs latency and high throughput performance by utilizing distributed control and optical feed-forward buffering in a modified Spanke architecture. Feasibility of a 256 port $Hipo λ aos$ layout with a four-packet buffering stage is experimentally demonstrated at 10 Gb/s, revealing error-free performance with a mean power penalty value of 2.19 dB. Simulation analysis is carried out for a 256 node system and eight traffic profiles; this analysis reveals a low latency value of only 605 ns, with throughput reaching 85% even when employing only two-packet buffers. Finally, the architecture’s scalability up to $1024 \times 1024$ designs is discussed, along with a power consumption analysis and a roadmap toward an integrated version of the switch.

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N. Terzenidis	https://orcid.org/0000-0001-8180-3953
M. Moralis-Pegios	https://orcid.org/0000-0002-9401-730X
G. Mourgias-Alexandris	https://orcid.org/0000-0002-9646-3119
T. Alexoudi	https://orcid.org/0000-0001-6722-201X

Switch Design	Port Number	Distr. Control	Contention Resolution	Data Rate (Gb/s)
NTT [20]	$270 \times 270$	No	No	10
Nagoya [21]	$1536 \times 1536$	No	No	10
A-Star [23]	$448 \times 448$	No	No	40
Data Vortex [43]	$10 K \times 10 K$	Yes	Deflection	10
OpSquare [24]	$2056 \times 2056$	Yes	EB-Input	40
Tonak-Lions [44]	$1024 \times 1024$	Yes	EB-Input	10
Petabit [49]	$1024 \times 1024$	No	EB-Input	10
Osmosis [46]	$2048 \times 2048$	No	EB-Input/Output	40
Iris [47]	$80 \times 80$	No	Optical delay line	40
$Hipo λ aos$ (this work)	$256 \times 256$ (up to $1024 \times 1024$ )	Yes	Optical delay line	10 (up to 40)

	Stage A	Stage B	Stage C	Total
SOA	$2 \times N^{2}$	0	$2 \times N$	$N \times (2 N + 2)$
EDFA	N	0	N	$2 \times N$
DML	$(K + 1) \times N^{2}$	0	$2 \times N^{2}$	$(K + 3) \times N^{2}$

Switch Design	Port Number	Distr. Control	Contention Resolution	Data Rate (Gb/s)
NTT [20]	$270 \times 270$	No	No	10
Nagoya [21]	$1536 \times 1536$	No	No	10
A-Star [23]	$448 \times 448$	No	No	40
Data Vortex [43]	$10 K \times 10 K$	Yes	Deflection	10
OpSquare [24]	$2056 \times 2056$	Yes	EB-Input	40
Tonak-Lions [44]	$1024 \times 1024$	Yes	EB-Input	10
Petabit [49]	$1024 \times 1024$	No	EB-Input	10
Osmosis [46]	$2048 \times 2048$	No	EB-Input/Output	40
Iris [47]	$80 \times 80$	No	Optical delay line	40
$Hipo λ aos$ (this work)	$256 \times 256$ (up to $1024 \times 1024$ )	Yes	Optical delay line	10 (up to 40)

	Stage A	Stage B	Stage C	Total
SOA	$2 \times N^{2}$	0	$2 \times N$	$N \times (2 N + 2)$
EDFA	N	0	N	$2 \times N$
DML	$(K + 1) \times N^{2}$	0	$2 \times N^{2}$	$(K + 3) \times N^{2}$

High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited]

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Journal of Optical Communications and Networking