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<< /S /GoTo /D (section.1) >>
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(Introduction)
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<< /S /GoTo /D (section.2) >>
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(Abstraction Layers need Time)
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<< /S /GoTo /D (section.3) >>
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(Microarchitecture)
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<< /S /GoTo /D (section.4) >>
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20 0 obj
(Memory Hierarchy)
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21 0 obj
<< /S /GoTo /D (subsection.4.1) >>
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24 0 obj
(Caches and Scratchpad Memories)
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25 0 obj
<< /S /GoTo /D (subsection.4.2) >>
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28 0 obj
(Dynamic Random Access Memory)
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29 0 obj
<< /S /GoTo /D (section.5) >>
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(On-chip Communication)
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33 0 obj
<< /S /GoTo /D (section.6) >>
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36 0 obj
(Instruction Set Architectures)
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37 0 obj
<< /S /GoTo /D (subsection.6.1) >>
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(Four Desirable Capabilities of an ISA)
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<< /S /GoTo /D (subsection.6.2) >>
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44 0 obj
(ISA Extensions)
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45 0 obj
<< /S /GoTo /D (section.7) >>
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48 0 obj
(Applications)
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49 0 obj
<< /S /GoTo /D (subsection.7.1) >>
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52 0 obj
(Mutual Exclusion)
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53 0 obj
<< /S /GoTo /D (subsection.7.2) >>
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(Message-dependent Deadlock Avoidance)
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<< /S /GoTo /D (section.8) >>
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(Conclusions)
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<< /S /GoTo /D (section.9) >>
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64 0 obj
(References)
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<< /S /GoTo /D [66 0 R /Fit ] >>
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