Browser Not SupportedA 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme | IEEE Conference Publication | IEEE Xplore

Notice: IEEE Xplore is unable to display this page because you may be using an incompatible or unsupported browser.

For the best experience, please upgrade to a newer, supported browser using the links below. If you cannot upgrade your browser, a temporary IEEE Xplore site is available for basic searches with links to full-text.