An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits | Frontiers of Computer Science Skip to main content

Advertisement

Log in

An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

  • Research Article
  • Published:
Frontiers of Computer Science Aims and scope Submit manuscript

Abstract

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed-Muller (MPRM) logic circuits, few studies have taken into account the polarity conversion sequence. In order to improve the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimization approach (FPOA) considering the polarity conversion sequence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set waiting for evaluation is obtained by using the proposed hybrid genetic algorithm (HGA); secondly, each of polarity in the polarity set is converted according to the best polarity conversion sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been presented for MCNC benchmark circuits. The experimental results show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity optimization of MPRM logic circuits compared with the traditional polarity optimization approach which neglects the polarity conversion sequence and the improved polarity optimization approach with heuristic technique.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Liang H, Xia Y S, Qian L B, Huang C L. Low power 3-input AND/XOR gate design. Journal of Computer-Aided Design & Computer Graphics, 2015, 27(5): 940–945

    Google Scholar 

  2. Wang X, Lu Y, Zhang Y. Probabilistic modeling during power estimation for mixed polarity Reed-Muller logic circuits. In: Proceedings of IEEE International Conference on Green Computing and Communications. 2013, 1414–1418

    Google Scholar 

  3. Wang P J, Wang Z H, Xu R. Conversion algorithm for MPRM expansion. Journals of Semiconductors, 2014, 35(3): 150–155

    MathSciNet  Google Scholar 

  4. Bu D L, Jiang J H. An efficient optimization algorithm for multi-output MPRM circuits with very large number of input variables. In: Proceedings of the 7th IEEE Joint International Information Technology and Artificial Intelligence Conference. 2014, 228–232

    Google Scholar 

  5. Geetha V, Devarajan N, Neelakantan P N. OR-Bridging fault analysis and diagnosis for exclusive-OR sum of products Reed-Muller canonical circuits. Journal of Computer Science, 2011, 7(5): 744–748

    Article  Google Scholar 

  6. Yu H Z, Jiang Z D, Wang P J. GA-DTPSO algorithm and its application in area optimization of mixed polarity XNOR/OR circuits. Journal of Computer-Aided Design & Computer Graphics, 2015, 27(5): 946–952

    Google Scholar 

  7. Li X W, Xia Y S, Wang L Y. An improved tabular-technique for mixpolarity. Journal of Ningbo University (NSEE), 2015, 28(1): 42–46

    Google Scholar 

  8. Li H, Wang P J, Dai J. Area minimization of MPRM circuits. In: Proceedings of the 8th International Conference on ASIC. 2009, 521–524

    Google Scholar 

  9. Almaini A E A, McKenzie L. Tabular techniques for generating kronecker expansions. IEE Proceedings — Computers and Digital Techniques, 1996, 143(4): 205–212

    Article  Google Scholar 

  10. Wang L, Almaini A E A. Exact minimisation of large multiple output FPRM functions. Computers and Digital Techniques, 2002, 149(5): 203–212

    Article  Google Scholar 

  11. Becker B, Drechsler R. OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms. In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors. 1994, 106–110

    Google Scholar 

  12. Purwar S. An efficient method of computing generalized Reed-Muller expansions from binary decision diagram. IEEE Transactions on Computers, 1991, 40(11): 1298–1301

    Article  Google Scholar 

  13. Sun F, Wang P J, Yu H Z. Ternary FPRM circuit area optimization based on genetic algorithm. Journal of Shandong University (Natural Science), 2013, 48(5): 51–56

    Google Scholar 

  14. Bu D L, Jiang J H. Dual logic based polarity conversion and optimization of mixed polarity RM circuits. Acta Electronica Sinica, 2015, 43(1): 79–85

    Google Scholar 

  15. Mudaliar D N, Modi N K. Unraveling travelling salesman problem by genetic algorithm using m-crossover operator. In: Proceedings of the International Conference on Signal Processing, Image Processing and Pattern Recognition (ICSIPR). 2013, 127–130

    Google Scholar 

  16. Thomson P, Miller J F. Optimisation techniques based on the use of genetic algorithms (Gas) for logic implementation on FPGAs. In: Proceedings of IEE Colloquium on Software Support and CAD Techniques for FPGAs. 1994

    Google Scholar 

  17. Drechsler R, Becker B, Gockel N. A genetic algorithm for the construction of small and highly testable OKFDD-circuits. In: Proceedings of the 1st Annual Conference on Genetic Programming. 1996, 473–478

    Google Scholar 

  18. Cong J, Ding Y Z. Combinational logic synthesis for LUT based field programmable gate arrays. ACM Transactions on Design Automation of Electronic Systems, 1996, 1(2): 145–204

    Article  Google Scholar 

  19. Yang M, Lai J M. Optimisation of mixed polarity Reed-Muller functions. Journal of Software, 2013, 8(11): 2770–2774

    Google Scholar 

  20. Wang P J, Li H, Wang Z H. MPRM expressions minimization based on simulated annealing genetic algorithm. In: Proceedings of the International Conference on Intelligent Systems and Knowledge Engineering (ISKE). 2010, 261–265

    Google Scholar 

  21. Jassani A, Urquhart N, Almaini A E A. Minimization of incompletely specified mixed polarity Reed-Muller functions using genetic algorithm. In: Proceedings of the 3rd International Conference on Signals, Circuits and Systems. 2009, 1–6

    Google Scholar 

  22. Yang M, Xu H Y, Almaini A E A. Optimization of mixed polarity Reed-Muller functions using genetic algorithm. In: Proceedings of the 3rd International Conference on Computer Research and Development (ICCRD). 2011, 293–296

    Google Scholar 

  23. Sun F, Wang P J, Yu H Z. Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm. In: Proceedings of the 10th IEEE International Conference on ASIC (ASICON). 2013, 1–4

    Google Scholar 

  24. Drechsler R, Becker B, Drechsler N. Genetic algorithm for minimisation of fixed polarity Reed-Muller expressions. Computers and Digital Techniques, 2000, 147(5): 349–353

    Article  Google Scholar 

  25. Wu W J, Wang P J, Zhang X Y. Notice of retraction search for the best polarity of fixed polarity Reed-Muller expression base on QGA. In: Proceedings of the 11th IEEE International Conference on Communication Technology. 2008, 343–346

    Google Scholar 

  26. Dai J, Zhang H H. A novel quantum genetic algorithm for area optimization of FPRM circuits. In: Proceedings of the 3rd International Symposium on Intelligent Information Technology Application. 2009, 408–411

    Google Scholar 

  27. Wang P J, Li H, Wang Z H. MPRM expressions minimization based on simulated annealing genetic algorithm. In: Proceedings of the International Conference on Intelligent Systems and Knowledge Engineering. 2010, 261–265

    Google Scholar 

  28. Chaudhury S, Chattopadhyay S. Output phase assignment for area and power optimization in multi-level multi-output combinational logic circuits. In: Proceedings of the Annual IEEE India Conference. 2006, 1–4

    Google Scholar 

  29. Almaini A E A, Mckenzie L. Tabular techniques for generating Kronecker expansions. Computers and Digital Techniques, 1996, 143(4): 205–212

    Article  Google Scholar 

  30. Zhang H H, Wang P J, Gu X S. Best polarity searching of FPRM circuits with heuristic technique. Journal of Circuits and Systems, 2009, 14(6): 24–28

    Google Scholar 

  31. Nguyen H D, Yoshihara I, Yamamori K, Yasunaga M. Implementation of an effective hybrid GA for large-scale traveling salesman problems. IEEE Transactions on Systems, Man, and Cybernetics, 2007, 37(1): 92–99

    Article  Google Scholar 

  32. Wang X, Lu Y, Zhang Y. Power optimization in logic synthesis for mixed polarity Reed-Muller logic circuits. The Computer Journal, 2015, 58(6): 1307–1313

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported by the National Natural Science Foundation of China (Grant Nos. 60973106, 61370059, 61232009 and 81571142), Beijing Natural Science Foundation (4152030), the National High Technology Research and Development Program (863 Project) of China (2011AA010404), Fundamental Research Funds for the Central Universities (YWF-15-GJSYS-085, YWF-14-JSJXY-14), Open Project Program of National Engineering Research Center for Science & Technology Resources Sharing Service (Beihang University), the fund of the State Key Laboratory of Computer Architecture (CARCH201507), and the fund of the State Key Laboratory of Software Development Environment (SKLSDE- 2014ZX-19).

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Limin Xiao or Xiang Wang.

Additional information

Zhenxue He is a PhD candidate in the School of Computer Science and Engineering, Beihang University, China. His research interests include low power integrated circuit design and optimization, multiple-valued logic circuits, and computer aided design. He is amember of ACM and China Computer Federation.

Limin Xiao is a professor of the School of Computer Science and Engineering, Beihang University, China. He is a senior membership of China Computer Federation. His main research areas are computer architecture, computer system software, high performance computing, virtualization and cloud computing.

Fei Gu is a PhD candidate in the School of Computer Science and Technology, Beihang University, China. He received the MS degree of computer science and technology from Nanjing University of Aeronautics and Astronautics, China in 2014 and the BS degree of software engineering from Yangzhou University, China in 2011. His research focuses on sensor network, healthcare system, and data mining.

Tongsheng Xia is an associate professor of the School of Electronic and Information Engineering, Beihang University, China. He received his PhD in microelectronics from University of Texas at Austin, USA in 2005. His research focuses on analog CMOS integrated circuit design and next generation storage device. He has published many top papers in international journals.

Shubin Su is a PhD candidate in the School of Computer Science and Technology, Beihang University, China. He received his MS degree of computer technology from Jiangxi University of Science and Technology, China in 2014. His research focuses on computer architecture, cloud computing, and data mining.

Zhisheng Huo is a PhD candidate in the School of Computer Science and Technology, Beihang University, China. He received his MS degree from College of Computer Science, Shenyang Aerospace University, China in 2012. His research focuses on big data storage and distributed storage system.

Rong Zhang is pursuing the master degree at the School of Electronics and Information Engineering, Beihang University, China. She received her BS of electronic information engineering from Shijiazhuang Railway University, China in 2013. Her research focuses on low power integrated circuit design and optimization.

Longbing Zhang is an associate professor of Institute of Computing Technology, Chinese Academy of Sciences, China. He is an associate director of Research Center for Microprocessor. He received his PhD in computer architecture from University of Science and Technology of China, China in 2002. His research focuses on microprocessor design and parallel processing.

Li Ruan is a lecturer of the School of Computer Science and Engineering, Beihang University, China. She is a senior membership of China Computer Federation. Her main research areas are virtualization and cloud computing, computer system software, and high performance computer.

Xiang Wang is a professor of the School of Electronic and Information Engineering, Beihang University, China. He is a senior membership of Chinese Institute of Electronics and Chinese Society of Micronano Technology. His main research areas are very large scale integration, micro-nano system, genetic circuits and aerospace information networks.

Electronic supplementary material

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

He, Z., Xiao, L., Gu, F. et al. An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits. Front. Comput. Sci. 11, 728–742 (2017). https://doi.org/10.1007/s11704-016-5259-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11704-016-5259-2

Keywords

Navigation