A hybrid hardware oriented motion estimation algorithm for HEVC/H.265 | Journal of Real-Time Image Processing Skip to main content
Springer Nature Link
Log in

A hybrid hardware oriented motion estimation algorithm for HEVC/H.265

  • Original Research Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process \(32\times 32\) CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD \((8192\times 4320)\) @ 78 fps.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Sullivan, G.J., Ohm, J., Han, W., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circ. Syst. Video Tech. 22(12), 1649–1668 (2012)

    Article  Google Scholar 

  2. Ye, Y., He, Y., Xiu, X.: Manipulating ultra-high definition video traffic. IEEE MultiMedia 22(3), 73–81 (2015)

    Article  Google Scholar 

  3. Luo, F., Wang, S., Wang, S., Zhang, X., Ma, S., Gao, W.: GPU based hierarchical motion estimation for high efficiency video coding. IEEE Trans. Multimedia 1, 1 (2018)

    Google Scholar 

  4. Gharavi, H., Mills, M.: Blockmatching motion estimation algorithms-new results. IEEE Trans. Circ. Syst. 37(5), 649–651 (1990)

    Article  Google Scholar 

  5. Yang, K., Sun, M., Wu, L.: A family of VLSI designs for the motion compensation block-matching algorithm. IEEE Trans. Circ. Sys. 36(10), 1317–1325 (1989)

    Article  Google Scholar 

  6. Shen, J.-F., Wang, T.-C., Chen, L.-G.: A novel low-power full-search block-matching motion-estimation design for H.263+. IEEE Trans. Circ. Syst. Video Tech. 11(7), 890–897 (2001)

    Article  Google Scholar 

  7. Tham, J.Y., Ranganath, S., Ranganath, M., Kassim, A.A.: A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Trans. Circ. Syst. Video Tech. 8(4), 369–377 (1998)

    Article  Google Scholar 

  8. Medhat, A., Shalaby, A., Sayed, M.S.: High throughput hardware implementation for motion estimation in HEVC encoder. In: Proc. IEEE 58th Int. Midwest Symp. on Circuits and Sys. (MWSCAS), pp. 1–4 (2015)

  9. Li, R., Zeng, B., Liou, M.L.: A new three-step search algorithm for block motion estimation. IEEE Trans. Circ. Syst. Video Tech. 4(4), 438–442 (1994)

    Article  Google Scholar 

  10. Ye, X., Ding, D., Yu, L.: A hardware-oriented IME algorithm and its implementation for HEVC. In: Proc. IEEE Visual Com. and Image Proc. Conference, pp. 205–208 (2014)

  11. Yee, H., Hu, A., Yu, H.: A novel modular systolic array architecture for full-search block matching motion estimation. IEEE Trans. Circ. Syst. Video Tech. 5(5), 407–416 (1995)

    Article  Google Scholar 

  12. Lai, Y.-K., Chen, L.-G.: A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm. IEEE Trans. Circ. Syst. Video Tech. 8(2), 124–127 (1998)

    Article  Google Scholar 

  13. de Vos, L., Stegherr, M.: Parameterizable VLSI architectures for the full-search block-matching algorithm. IEEE Trans. Circ. Syst. 36(10), 1309–1316 (1989)

    Article  Google Scholar 

  14. Roma, N., Sousa, L.: Efficient and configurable full-search block-matching processors. IEEE Trans. Circ. Syst. Video Tech. 12(12), 1160–1167 (2002)

    Article  Google Scholar 

  15. Jain, J., Jain, A.: Displacement measurement and its application in interframe image coding. IEEE Trans. Commun. 29(12), 1799–1808 (1981)

    Article  Google Scholar 

  16. Koga, T., Iinuma, K., Hirano, A., Iijima, Y., Ishiguro, T.: Motion compensated interframe coding for video conferencing. In: Proc. Nat. Telecommun. Conf. New Orleans, pp. 5.3.1–5.3.5 (1981)

  17. Srinivasan, R., Rao, K.: Predictive coding based on efficient motion estimation. IEEE Trans. Commun. 33(8), 888–896 (1985)

    Article  Google Scholar 

  18. Ghanbari, M.: The cross-search algorithm for motion estimation (image coding). IEEE Trans. Commun. 38(7), 950–953 (1990)

    Article  Google Scholar 

  19. Po, L.-M., Ma, W.-C.: A novel four-step search algorithm for fast block motion estimation. IEEE Trans. Circ. Syst. Video Tech. 6(3), 313–317 (1996)

    Article  Google Scholar 

  20. Liu, L.-K., Feig, E.: A block-based gradient descent search algorithm for block motion estimation in video coding. IEEE Trans. Circ. Syst. Video Tech. 6(4), 419–422 (1996)

    Article  Google Scholar 

  21. Zhu, C., Lin, X., Chau, L.-P.: Hexagon-based search pattern for fast block motion estimation. IEEE Trans. Circ. Syst. Video Tech. 12(5), 349–355 (2002)

    Article  Google Scholar 

  22. Boyce, J., Hong, D., Jang, W.: Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11. In: HEVC HM10 reference software (JCTVC-l1010), 12th meeting: Geneva, CH, pp. 14–23 (2013)

  23. Ndili, O., Ogunfunmi, T.: Fast algorithm and efficient architecture for integer and fractional motion estimation. J. Signal Proc. Syst. 75(1), 55–64 (2014)

    Article  Google Scholar 

  24. Nie, Y., Ma, K.K.P.: Adaptive rood pattern search for fast block-matching motion estimation. IEEE Trans. Image Process. 11(12), 1442–1449 (2002)

    Article  Google Scholar 

  25. Tourapis, A., Au, O. C., Liou, M.: Predictive motion vector field adaptive search technique (PMVFAST)—enhancing block based motion estimation. In: Proc. of SPIE—the international society for optical engineering (2001)

  26. Wong, H. -M., Au, O. C., Ho, C.-W., Yip, S. -K.: Enhanced predictive motion vector field adaptive search technique (E-PMVFAST)-based on future MV prediction. In: Proc. IEEE international conference on multimedia and expo (2005)

  27. Purnachand, N., Alves, L. N., Navarro, A.: Fast motion estimation algorithm for HEVC. In: Proc. IEEE Second Int. Conf. on Consumer Electronics—Berlin (ICCE-Berlin), pp. 34–37 (2012)

  28. Khemiri, R., Kibeya, H., Loukil, H., Sayadi, F.E., Atri, M., Masmoudi, N.: Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA. Analog Integr. Circ. Signal Process. 94(2), 259–276 (2018)

    Article  Google Scholar 

  29. Dinh, C., Nguyen, T., Pham, C., Nguyen, P., Duong, D., Phung, H., Pham, T., Nguyen, T.: A novel parallel hardware architecture for inter motion estimation in HEVC. J. Telecom. Electronic Comput. Eng. 9, 1 (2017)

    Google Scholar 

  30. Thang, N.V., Dac Tung, V., Hoan, N.D.: An optimized hardware design of Integer Motion Estimation HEVC for encoding 8K video. In: Proc. 4th NAFOSTED Conference on Information and Computer Science, pp. 319–324(2017)

  31. Nguyen, P., Tran, H., Nguyen, H., Nguyen, X. -N., Vo, C., Nguyen, B., Ngo, V. -D., Nguyen, V. -T.: Asymmetric diamond search pattern for motion estimation in HEVC. In: Proc. IEEE Fifth international conference on communications and electronics (ICCE), pp. 434–439 (2014)

  32. Byun, J., Jung, Y., Kim, J.: Design of integer motion estimator of HEVC for asymmetric motion-partitioning mode and 4K-UHD. Electron. Lett. 49(18), 1142–1143 (2013)

    Article  Google Scholar 

  33. Singh, K., Ahamed, S.R.: Low power motion estimation algorithm and architecture of HEVC/H.265 for consumer applications. IEEE Trans. Consumer Electron. 1, 1 (2018)

    Google Scholar 

  34. Li, X., Wang, R., Wang, W., Wang, Z., Dong, S.: Fast motion estimation methods for HEVC. In: Proc. IEEE int. symp. on broadband mult. systems and broadcasting, pp. 1–4 (2014)

  35. Singh, K., Ahamed, S.R.: Computationally efficient motion estimation algorithm for HEVC. J. Signal Process. Syst. 90(12), 1713–1727 (2018)

    Article  Google Scholar 

  36. Jou, S., Chang, S., Chang, T.: Fast motion estimation algorithm and design for real time QFHD high efficiency video coding. IEEE Trans. Circ. Syst. Video Tech. 25(9), 1533–1544 (2015)

    Article  Google Scholar 

  37. Zhou, D., Zhou, J., He, G., Goto, S.: A 1.59 Gpixel/s motion estimation processor with -211 to +211 search range for UHDTV video encoder. IEEE J. Solid-State Circ. 49(4), 827–837 (2014)

    Article  Google Scholar 

  38. Sinangil, M.E., Sze, V., Zhou, M., Chandrakasan, A.P.: Cost and coding efficient motion estimation design considerations for high efficiency video coding (HEVC) standard. IEEE J. Solid-State Circ. 7(6), 1017–1028 (2013)

    Google Scholar 

  39. Bjontegaard, G.: Calculation of average PSNR differences between RD curves. In: ITUT-T Q6/SG16, Doc. VCEG-M33, Tech. Rep. (2001)

  40. Pakdaman, F., Gabbouj, M., Hashemi, M. R., Ghanbari, M.: Fast motion estimation algorithm with efficient memory access for HEVC hardware encoders. In: Proc. 7th European workshop on visual information processing (EUVIP), pp. 1–5 (2018)

  41. Jia, L., Tsui, C., Au, O.C., Jia, K.: A low-power motion estimation architecture for HEVC based on a new sum of absolute difference computation. IEEE Trans. Circ. Syst. Video Tech. 1, 1 (2018)

    Google Scholar 

  42. Kim, T.S., Rhee, C.E., Lee, H.: Fast hardware-based ime with idle cycle and computational redundancy reduction. IEEE Trans. Circ. Syst. Video Tech. 1, 1 (2019)

    Google Scholar 

  43. Tseng, Y., Shen, C.: The design and implementation of a highly efficient motion estimation engine for HEVC Systems. In: Proc. IEEE international symposium on circuits and systems (ISCAS), pp. 1–5 (2019)

  44. Joginipelly, A.K., Charalampidis, D.: An efficient circuit for error reduction in logarithmic multiplication for filtering applications. Int. J. Circ. Theory Appl. 48(5), 809–815 (2020)

    Article  Google Scholar 

  45. Joginipelly, A.K., Varela, A., Charalampidis, D., Schott, R., Fitzsimmons, Z. : Efficient FPGA implementation of steerable Gaussian smoothers. In: Proc. 44th Southeastern Symposium on System Theory (SSST), pp. 78–82 (2012)

  46. Joginipelly, A.K.: Efficient fpga architectures for separable filters and logarithmic multipliers and automation of fish feature extraction using gabor filters. In: University of New Orleans Theses and Dissertations, pp. 1876 (2014)

  47. Joginipelly, A.K., Charalampidis, D.: Efficient separable convolution using field programmable gate arrays. Microprocess. Microsyst. 71, 102852 (2019)

    Article  Google Scholar 

  48. He, G., Zhou, D., Li, Y., Chen, Z., Zhang, T., Goto, S.: Fast hardware-based IME with idle cycle and computational redundancy reduction. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(12), 3138–3142 (2015)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Meghalaya, 793003, India

    Sushanta Gogoi & Rangababu Peesapati

Authors
  1. Sushanta Gogoi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rangababu Peesapati
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sushanta Gogoi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Electronic supplementary material

Below is the link to the electronic supplementary material.

Supplementary material 1 (pdf 185 KB)

Supplementary material 2 (pdf 3 KB)

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gogoi, S., Peesapati, R. A hybrid hardware oriented motion estimation algorithm for HEVC/H.265. J Real-Time Image Proc 18, 953–966 (2021). https://doi.org/10.1007/s11554-020-01056-w

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-020-01056-w

Keywords

Search

Navigation