Chip design with machine learning: a survey from algorithm perspective | Science China Information Sciences Skip to main content

Advertisement

Springer Nature Link
Log in

Chip design with machine learning: a survey from algorithm perspective

  • Review
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

Chip design with machine learning (ML) has been widely explored to achieve better designs, lower runtime costs, and no human-in-the-loop process. However, with tons of work, there is a lack of clear links between the ML algorithms and the target problems, causing a huge gap in understanding the potential and possibility of ML in future chip design. This paper comprehensively surveys existing studies in chip design with ML from an algorithm perspective. To achieve this goal, we first propose a novel and systematical taxonomy that divides target problems in chip design into three categories. Then, to solve the target problems with ML algorithms, we formulate the three categories as three ML problems correspondingly. Based on the taxonomy, we conduct a comprehensive survey in terms of target problems based on different ML algorithms. Finally, we conclude three key challenges for existing studies and highlight several insights for the future development of chip design with machine learning. By constructing a clear link between chip design problems and ML solutions, we hope the survey can shed light on the road to chip design intelligence from previous chip design automation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

References

  1. Chen Y, Du Z, Guo Q, et al. From chip design to chip learning (in Chinese). Bull Chin Academy Sci, 2022, 37: 15–23

    Google Scholar 

  2. Huang G, Hu J, He Y, et al. Machine learning for electronic design automation: a survey. ACM Trans Des Autom Electron Syst, 2021, 26: 1–46

    Article  Google Scholar 

  3. Lopera D S, Servadei L, Kiprit G N, et al. A comprehensive survey on electronic design automation and graph neural networks: theory and applications. ACM Trans Design Autom Electron Syst, 2023, 28: 1–27

    Google Scholar 

  4. Yan J, Lyu X, Cheng R, et al. Towards machine learning for placement and routing in chip design: a methodological overview. 2022. ArXiv:2202.13564

    Google Scholar 

  5. Cristescu M C. Machine learning techniques for improving the performance metrics of functional verification. Sci Technol, 2021, 24: 99–116

    Google Scholar 

  6. Tang H, Liu G, Chen X, et al. A survey on Steiner tree construction and global routing for VLSI design. IEEE Access, 2020, 8: 68593–68622

    Article  Google Scholar 

  7. Xie Z, Pan J, Chang C C, et al. The dark side: security concerns in machine learning for EDA. 2022. ArXiv:2022.10597

    Google Scholar 

  8. Scarselli F, Gori M, Tsoi A C, et al. The graph neural network model. IEEE Trans Neural Netw, 2008, 20: 61–80

    Article  Google Scholar 

  9. Goodfellow I, Pouget-Abadie J, Mirza M, et al. Generative adversarial networks. Commun ACM, 2020, 63: 139–144

    Article  Google Scholar 

  10. He K, Zhang X, Ren S, et al. Deep residual learning for image recognition. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016. 770–778

    Google Scholar 

  11. Vaswani A, Shazeer N, Parmar N, et al. Attention is all you need. In: Proceedings of the 31st International Conference on Neural Information Processing Systems, Long Beach, 2017. 6000–6010

    Google Scholar 

  12. Watkins C J C H, Dayan P. Q-learning. Machine learning. 1992, 8: 279–292

    Article  MATH  Google Scholar 

  13. Mnih V, Kavukcuoglu K, Silver D, et al. Playing atari with deep reinforcement learning. 2013. ArXiv:1312.5602

    Google Scholar 

  14. Ferianc M, Fan H X, Chu R, et al. Improving performance estimation for FPGA-based accelerators for convolutional neural networks. In: Proceedings of the 16th International Symposium on Applied Reconfigurable Computing, Toledo, 2020. 3–13

    Google Scholar 

  15. Dai S, Zhou Y, Zhang H, et al. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In: Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, 2018. 129–132

    Google Scholar 

  16. Zhao J, Liang T, Sinha S, et al. Machine learning based routing congestion prediction in FPGA high-level synthesis. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Florence, 2019. 1130–1135

    Google Scholar 

  17. Makrani H M, Sayadi H, Mohsenin T, et al. XPPE: cross-platform performance estimation of hardware accelerators using machine learning. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, Tokyo, 2019. 727–732

    Chapter  Google Scholar 

  18. Makrani H M, Farahmand F, Sayadi H, et al. Pyramid: machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design. In: Proceedings of the 29th International Conference on Field-Programmable Logic and Applications, Barcelona, 2019. 397–403

    Google Scholar 

  19. De S, Shafique M, Corporaal H. Delay prediction for ASIC HLS: comparing graph-based and nongraph-based learning models. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2023, 42: 1133–1146

    Article  Google Scholar 

  20. Que Y H, Kapre N, Ng H, et al. Improving classification accuracy of a machine learning approach for FPGA timing closure. In: Proceedings of the IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines, Washington, 2016. 80–83

    Google Scholar 

  21. Liu H Y, Carloni L P. On learning-based methods for design-space exploration with high-level synthesis. In: Proceedings of the 50th Annual Design Automation Conference, New York, 2013. 1–7

    Google Scholar 

  22. Mahapatra A, Schafer B C. Machine-learning based simulated annealer method for high level synthesis design space exploration. In: Proceedings of the Electronic System Level Synthesis Conference, San Francisco, 2014. 1–6

    Google Scholar 

  23. Kwon J, Carloni L P. Transfer learning for design-space exploration with high-level synthesis. In: Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD, Virtual, 2020. 163–168

    Chapter  Google Scholar 

  24. Wu N, Xie Y, Hao C. IronMan: GNN-assisted design space exploration in high-level synthesis via reinforcement learning. In: Proceedings of the 2021 on Great Lakes Symposium on VLSI, Virtual, 2021. 39–44

    Chapter  Google Scholar 

  25. Cheng W K, Guo Y Y, Wu C S. Evaluation of routability-driven macro placement with machine-learning technique. In: Proceedings of the 7th International Symposium on Next-Generation Electronics, Taipei, 2018. 1–3

    Google Scholar 

  26. Huang Y H, Xie Z, Fang G Q, et al. Routability-driven macro placement with embedded CNN-based prediction model. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Florence, 2019. 180–185

    Google Scholar 

  27. Chan W T J, Chung K Y, Kahng A B, et al. Learning-based prediction of embedded memory timing failures during initial floorplan design. In: Proceedings of the 21st Asia and South Pacific Design Automation Conference, Macao, 2016. 178–185

    Google Scholar 

  28. Zhang S Z, Zhao Z Y, Feng C C, et al. A machine learning framework with feature selection for floorplan acceleration in ic physical design. J Comput Sci Technol, 2020, 35: 468–474

    Article  Google Scholar 

  29. Shanthi J, Rani D G N, Rajaram S. A C4.5 decision tree classifier based floorplanning algorithm for system-on-chip design. MicroElectron J, 2022, 121: 105361

    Article  Google Scholar 

  30. He Z, Ma Y, Zhang L, et al. Learn to floorplan through acquisition of effective local search heuristics. In: Proceedings of IEEE 38th International Conference on Computer Design, Hartford, 2020. 324–331

    Google Scholar 

  31. Oh C, Bondesan R, Kianfar D, et al. Bayesian optimization for macro placement. 2022. ArXiv:2207.08398

    Google Scholar 

  32. Liu Y, Ju Z, Li Z, et al. Floorplanning with graph attention. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1303–1308

    Chapter  Google Scholar 

  33. Liu Y, Ju Z, Li Z, et al. GraphPlanner: floorplanning with graph neural network. ACM Trans Des Autom Electron Syst, 2023, 28: 1–24

    Google Scholar 

  34. Mirhoseini A, Goldie A, Yazgan M, et al. Chip placement with deep reinforcement learning. 2020. ArXiv:2004.10746

    Google Scholar 

  35. Xu Q, Geng H, Chen S, et al. GoodFloorplan: graph convolutional network and reinforcement learning-based floorplanning. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2022, 41: 3492–3502

    Article  Google Scholar 

  36. Amini M, Zhang Z, Penmetsa S, et al. Generalizable floorplanner through corner block list representation and hypergraph embedding. In: Proceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, 2022. 2692–2702

    Google Scholar 

  37. Chang F C, Tseng Y W, Yu Y W, et al. Flexible multiple-objective reinforcement learning for chip placement. 2022. ArXiv:2204.06407

    Google Scholar 

  38. Barboza E C, Shukla N, Chen Y, et al. Machine learning-based pre-routing timing prediction with reduced pessimism. In: Proceedings of the 56th Annual Design Automation Conference, Las Vegas, 2019. 1–6

    Google Scholar 

  39. Ho C T, Kahng A B. IncPIRD: fast learning-based prediction of incremental IR drop. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Westminster, 2019. 1–8

    Google Scholar 

  40. Guo Z, Liu M, Gu J, et al. A timing engine inspired graph neural network model for pre-routing slack prediction. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1207–1212

    Chapter  Google Scholar 

  41. Yang T, He G, Cao P. Pre-routing path delay estimation based on transformer and residual framework. In: Proceedings of the 27th Asia and South Pacific Design Automation Conference, Taipei, 2022. 184–189

    Google Scholar 

  42. Tabrizi A F, Darav N K, Xu S, et al. A machine learning framework to identify detailed routing short violations from a placed netlist. In: Proceedings of the 55th Annual Design Automation Conference, San Francisco, 2018. 1–6

    Google Scholar 

  43. Xie Z, Huang Y H, Fang G Q, et al. RouteNet: routability prediction for mixed-size designs using convolutional neural network. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Diego, 2018. 1–8

    Google Scholar 

  44. Liang R, Xiang H, Pandey D, et al. DRC hotspot prediction at sub-10nm process nodes using customized convolutional network. In: Proceedings of the International Symposium on Physical Design, Taipei, 2020. 135–142

    Google Scholar 

  45. Liu S, Sun Q, Liao P, et al. Global placement with deep learning-enabled explicit routability optimization. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2021. 1821–1824

    Google Scholar 

  46. Ghose A, Zhang V, Zhang Y, et al. Generalizable cross-graph embedding for GNN-based congestion prediction. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Munich, 2021. 1–9

    Google Scholar 

  47. Wang B, Shen G, Li D, et al. LHNN: lattice hypergraph neural network for VLSI congestion prediction. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1–6

    Google Scholar 

  48. Xie Z, Ren H, Khailany B, et al. PowerNet: transferable dynamic IR drop estimation via maximum convolutional neural network. In: Proceedings of the 25th Asia and South Pacific Design Automation Conference, Beijing, 2020. 13–18

    Google Scholar 

  49. Zhou H, Jin W, Tan S X D. GridNet: fast data-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks. In: Proceedings of the 39th International Conference on Computer-Aided Design, Virtual, 2020. 1–9

    Google Scholar 

  50. Cao Y, Kahng A B, Li J, et al. Learning-based prediction of package power delivery network quality. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, Tokyo, 2019. 160–166

    Chapter  Google Scholar 

  51. Hyun D, Fan Y, Shin Y. Accurate wirelength prediction for placement-aware synthesis through machine learning. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Florence, 2019. 324–327

    Google Scholar 

  52. Lu Y C, Pentapati S, Lim S K. The law of attraction: affinity-aware placement optimization using graph neural networks. In: Proceedings of the International Symposium on Physical Design, Virtual, 2021. 7–14

    Google Scholar 

  53. Guo Z, Lin Y. Differentiable-timing-driven global placement. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1315–1320

    Chapter  Google Scholar 

  54. Zhou X, Ye J, Pui C W, et al. Heterogeneous graph neural network-based imitation learning for gate sizing acceleration. In: Proceedings of International Conference on Computer-Aided Design, San Diego, 2022. 1–9

    Google Scholar 

  55. Vashisht D, Rampal H, Liao H, et al. Placement in integrated circuits using cyclic reinforcement learning and simulated annealing. 2020. ArXiv:2011.07577

    Google Scholar 

  56. Agnesina A, Chang K, Lim S K. VLSI placement parameter optimization using deep reinforcement learning. In: Proceedings of the 39th International Conference on Computer-Aided Design, Virtual, 2020. 1–9

    Google Scholar 

  57. Lu Y C, Nath S, Khandelwal V, et al. RL-Sizer: VLSI gate sizing for timing optimization using deep reinforcement learning. In: Proceedings of the 58th ACM/IEEE Design Automation Conference, San Francisco, 2021. 733–738

    Google Scholar 

  58. Lin Y, Dhar S, Li W, et al. DREAMPlace: deep learning toolkit-enabled GPU acceleration for modern VLSI placement. In: Proceedings of the 56th Annual Design Automation Conference, Las Vegas, 2019. 1–6

    Google Scholar 

  59. Liu L, Fu B, Wong M D F, et al. Xplace: an extremely fast and extensible global placement framework. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1309–1314

    Chapter  Google Scholar 

  60. Nath S, Pradipta G, Hu C, et al. Generative self-supervised learning for gate sizing. In: Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, 2022. 1331–1334

    Chapter  Google Scholar 

  61. Chhabria V A, Kahng A B, Kim M, et al. Template-based PDN synthesis in floorplan and placement using classifier and CNN techniques. In: Proceedings of the 25th Asia and South Pacific Design Automation Conference, Beijing, 2020. 44–49

    Google Scholar 

  62. Qi Z, Cai Y, Zhou Q. Accurate prediction of detailed routing congestion using supervised data learning. In: Proceedings of IEEE 32nd International Conference on Computer Design, Seoul, 2014. 97–103

    Google Scholar 

  63. Zhou Q, Wang X, Qi Z, et al. An accurate detailed routing routability prediction model in placement. In: Proceedings of the 6th Asia Symposium on Quality Electronic Design, Kula Lumpur, 2015. 119–122

    Google Scholar 

  64. He Y, Bao F S. Circuit routing using Monte Carlo tree search and deep neural networks. 2020. ArXiv:2006.13607

    Google Scholar 

  65. Chen J, Kuang J, Zhao G, et al. PROS: a plug-in for routability optimization applied in the state-of-the-art commercial EDA tool using deep learning. In: Proceedings of the 39th International Conference on Computer-Aided Design, Virtual, 2020. 1–8

    Google Scholar 

  66. Liao H, Dong Q, Dong X, et al. Attention routing: track-assignment detailed routing using attention-based reinforcement learning. In: Proceedings of International Design Engineering Technical Conferences and Computers and Information in Engineering Conference, St. Louis, 2020. 84003: V11AT11A002

    Google Scholar 

  67. Ju X, Zhu K, Lin Y, et al. Asynchronous multi-nets detailed routing in VLSI using multi-agent reinforcement learning. In: Proceedings of the 7th IEEE International Conference on Network Intelligence and Digital Content, Beijing, China, 2021. 250–254

    Google Scholar 

  68. Lin Y, Qu T, Lu Z, et al. Asynchronous reinforcement learning framework and knowledge transfer for net-order exploration in detailed routing. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2022, 41: 3132–3142

    Article  Google Scholar 

  69. Utyamishev D, Partin-Vaisband I. Late breaking results: a neural network that routes ICs. In: Proceedings of the 57th ACM/IEEE Design Automation Conference, Virtual, 2020. 1–2

    Google Scholar 

  70. Hosny A, Hashemi S, Shalan M, et al. DRiLLS: deep reinforcement learning for logic synthesis. In: Proceedings of the 25th Asia and South Pacific Design Automation Conference, Beijing, 2020. 581–586

    Google Scholar 

  71. Grosnit A, Malherbe C, Tutunov R, et al. BOiLS: Bayesian optimisation for logic synthesis. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2022. 1193–1196

    Google Scholar 

  72. Floridi L, Chiriatti M. GPT-3: its nature, scope, limits, and consequences. Minds Machines, 2020, 30: 681–694

    Article  Google Scholar 

  73. Silver D, Huang A, Maddison C J, et al. Mastering the game of Go with deep neural networks and tree search. Nature, 2016, 529: 484–489

    Article  Google Scholar 

  74. Jumper J, Evans R, Pritzel A, et al. Highly accurate protein structure prediction with AlphaFold. Nature, 2021, 596: 583–589

    Article  Google Scholar 

  75. Fawzi A, Balog M, Huang A, et al. Discovering faster matrix multiplication algorithms with reinforcement learning. Nature, 2022, 610: 47–53

    Article  MATH  Google Scholar 

  76. Ambasana N, Gope D, Mutnury B, et al. Application of artificial neural networks for eye-height/width prediction from S-parameters. In: Proceedings of IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014. 99–102

    Google Scholar 

  77. Lu T, Wu K, Yang Z, et al. High-speed channel modeling with deep neural network for signal integrity analysis. In: Proceedings of the 26th Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, 2017. 1–3

    Google Scholar 

  78. Kwon Y, Jung J, Han I, et al. Transient clock power estimation of pre-CTS netlist. In: Proceedings of IEEE International Symposium on Circuits and Systems, Florence, 2018. 1–4

    Google Scholar 

  79. Lee Y Y, Ruan S J, Chen P C. Predictable coupling effect model for global placement using generative adversarial networks with an ordinary differential equation solver. IEEE Trans Circuits Syst II, 2021, 69: 2261–2265

    Google Scholar 

  80. Xie Z, Liang R, Xu X, et al. Net2: a graph attention network method customized for pre-placement net length estimation. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, Taipei, 2021. 671–677

    Google Scholar 

  81. Neto W L, Austin M, Temple S, et al. LSOracle: a logic synthesis framework driven by artificial intelligence. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Westminster, 2019. 1–6

    Google Scholar 

  82. Ma Y, Ren H, Khailany B, et al. High performance graph convolutional networks with applications in testability analysis. In: Proceedings of the 56th Annual Design Automation Conference, Las Vegas, 2019. 1–6

    Google Scholar 

  83. Gad M, Aboelmaged M, Mashaly M, et al. Efficient sequence generation for hardware verification using machine learning. In: Proceedings of the 28th IEEE International Conference on Electronics, Circuits, and Systems, Dubai, 2021. 1–5

    Google Scholar 

  84. Haaswijk W, Collins E, Seguin B, et al. Deep learning for logic optimization algorithms. In: Proceedings of IEEE International Symposium on Circuits and Systems, Florence, 2018. 1–4

    Google Scholar 

  85. Zhu K, Liu M, Chen H, et al. Exploring logic optimizations with reinforcement learning and graph convolutional network. In: Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD, Virtual, Iceland, 2020. 145–150

    Google Scholar 

  86. Shi Z, Li M, Khan S, et al. DeepTPI: test point insertion with deep reinforcement learning. 2022. ArXiv:2206.06975

    Google Scholar 

  87. Balog M, Gaunt A L, BrockschmidtM, et al. DeepCoder: learning to write programs. In: Proceedings of the 5th International Conference on Learning Representations, Toulon, 2017. 1–21

    Google Scholar 

  88. Lu Y C, Lee J, Agnesina A, et al. GAN-CTS: a generative adversarial framework for clock tree prediction and optimization. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Westminster, 2019. 1–8

    Google Scholar 

  89. Koh S, Kwon Y, Shin Y. Pre-layout clock tree estimation and optimization using artificial neural network. In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, 2020. 193–198

    Chapter  Google Scholar 

  90. Zheng X, Eder K, Blackmore T. A neural network based novel test selector. 2022. ArXiv:2207.00445

    Google Scholar 

  91. Donno M, Ivaldi A, Benini L, et al. Clock-tree power optimization based on RTL clock-gating. In: Proceedings of the 40th annual Design Automation Conference, Anaheim, 2003. 622–627

    Chapter  Google Scholar 

  92. Chan H G, Goh P. Neural networks for eye height and eye width prediction with an improved adaptive sampling algorithm. In: Proceedings of the 17th Asian Simulation Conference, Melaka, 2017. 189–201

    Google Scholar 

  93. Enzler R, Jeger T, Cottet D, et al. High-level area and performance estimation of hardware building blocks on FPGAs. In: Proceedings of Field-Programmable Logic and Applications, Villach, 2000. 525–534

    Google Scholar 

  94. Qi Z, Cai Y, Zhou Q, et al. VFGR: a very fast parallel global router with accurate congestion modeling. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, Tokyo, 2014. 525–530

    Google Scholar 

  95. Chang H, Sapatnekar S S. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2004. 621–625

    Google Scholar 

  96. Chen T, Guestrin C. XGBoost: a scalable tree boosting system. In: Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, New York, 2016. 785–794

    Chapter  Google Scholar 

  97. Salvatori T, Song Y, Xu Z, et al. Reverse differentiation via predictive coding. In: Proceedings of the 36th AAAI Conference on Artificial Intelligence, Virtual, 2022. 8150–8158

    Google Scholar 

  98. Ororbia A, Kifer D. The neural coding framework for learning generative models. Nat Commun, 2022, 13: 2064

    Article  Google Scholar 

  99. Hinton G. The forward-forward algorithm: some preliminary investigations. 2022. ArXiv:2212.13345

    Google Scholar 

  100. Ororbia A, Mali A. The predictive forward-forward algorithm. 2023. ArXiv:2301.01452

    Google Scholar 

  101. Spindler P, Johannes F M. Fast and accurate routing demand estimation for efficient routability-driven placement. In: Proceedings of the Conference on Design, Automation and Test in Europe, Nice, 2007. 1–6

    Google Scholar 

  102. Ronneberger O, Fischer P, Brox T. U-Net: convolutional networks for biomedical image segmentation. In: Proceedings of the 18th International Conference on Medical Image Computing and Computer-Assisted Intervention, Munich, 2015. 234–241

    Google Scholar 

  103. Huang C C, Lee H Y, Lin B Q, et al. NTUplace4dr: a detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2017, 37: 669–681

    Article  Google Scholar 

  104. Grover A, Leskovec J. Node2vec: scalable feature learning for networks. In: Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, San Francisco, 2016. 855–864

    Chapter  Google Scholar 

  105. Tang J, Qu M, Wang M, et al. LINE: large-scale information network embedding. In: Proceedings of the 24th International Conference on World Wide Web, Florence, 2015. 1067–1077

    Chapter  Google Scholar 

  106. Perozzi B, Al-Rfou R, Skiena S. DeepWalk: online learning of social representations. In: Proceedings of the 20th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, New York, 2014. 701–710

    Chapter  Google Scholar 

  107. Isola P, Zhu J Y, Zhou T, et al. Image-to-image translation with conditional adversarial networks. In: Proceedings of Conference on Computer Vision and Pattern Recognition, Honolulu, 1125–1134

  108. Fang Y C, Lin H Y, Sui M Y, et al. Machine-learning-based dynamic IR drop prediction for ECO. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Diego, 2018. 1–7

    Google Scholar 

  109. Sun Z, Yu S, Zhou H, et al. EMSpice: physics-based electromigration check using coupled electronic and stress simulation. IEEE Trans Device Mater Relib, 2020, 20: 376–389

    Article  Google Scholar 

  110. Dai K R, Liu W H, Li Y L. NCTU-GR: efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-D global routing. IEEE Trans VLSI Syst, 2011, 20: 459–472

    Article  Google Scholar 

  111. Hu B, Marek-Sadowska M. Wire length prediction based clustering and its application in placement. In: Proceedings of the 40th annual Design Automation Conference, Anaheim, 2003. 800–805

    Chapter  Google Scholar 

  112. Kahng A B, Reda S. Intrinsic shortest path length: a new, accurate a priori wirelength estimator. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2005. 173–180

    Google Scholar 

  113. Fathi B, Behjat L, Rakai L M. A pre-placement net length estimation technique for mixed-size circuits. In: Proceedings of the 11th International Workshop on System Level Interconnect Prediction, Francisco, 2009. 45–52

    Chapter  Google Scholar 

  114. Freund Y, Schapire R, Abe N. A short introduction to boosting. J-Japan Soc Artif Intell, 1999, 14: 1612

    Google Scholar 

  115. Hastie T, Tibshirani R, Friedman J H, et al. The Elements of Statistical Learning: Data Mining, Inference, and Prediction. New York: Springer, 2009. 1–698

    MATH  Google Scholar 

  116. Krishnamurthy B. A dynamic programming approach to the test point insertion problem. In: Proceedings of the 24th ACM/IEEE Design Automation Conference, Miami Beach, 1987. 695–705

    Chapter  Google Scholar 

  117. Yu K, Bi J, Tresp V. Active learning via transductive experimental design. In: Proceedings of the 23rd International Conference on Machine Learning, Pittsburgh, 2006. 1081–1088

    Chapter  Google Scholar 

  118. Quinlan J. C4.5: Programs for Machine Learning. San Francisco: Morgan Kaufmann Publishers, 1993. 155–164

    Google Scholar 

  119. Flach G, Reimann T, Posser G, et al. Effective method for simultaneous gate sizing and V th assignment using lagrangian relaxation. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2014, 33: 546–557

    Article  Google Scholar 

  120. Browne C B, Powley E, Whitehouse D, et al. A survey of Monte Carlo tree search methods. IEEE Trans Comput Intell AI Games, 2012, 4: 1–43

    Article  Google Scholar 

  121. Yang W, Wang L, Mishchenko A. Lazy man's logic synthesis. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2012. 597–604

    Chapter  Google Scholar 

  122. Amarú L, Gaillardon P E, de Micheli G. The EPFL combinational benchmark suite. In: Proceedings of the 24th International Workshop on Logic & Synthesis, Mountain View, 2015. 1–5

    Google Scholar 

  123. Niu S, Chen S, Guo H, et al. Generalized value iteration networks: life beyond lattices. In: Proceedings of the 32nd AAAI Conference on Artificial Intelligence, New Orleans, 2018. 6246–6253

    Google Scholar 

  124. Sykora Q, Ren M, Urtasun R. Multi-agent routing value iteration network. In: Proceedings of the 37th International Conference on Machine Learning, Virtual, 2020. 9300–9310

    Google Scholar 

  125. Qu T, Lin Y, Lu Z, et al. Asynchronous reinforcement learning framework for net order exploration in detailed routing. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2021. 1815–1820

    Google Scholar 

  126. Ansel J, Kamil S, Veeramachaneni K, et al. OpenTuner: an extensible framework for program autotuning. In: Proceedings of the 23rd International Conference on Parallel Architectures and Compilation, Edmonton, 2014. 303–316

    Chapter  Google Scholar 

  127. Schotten C, Meyr H. Test point insertion for an area efficient BIS. In: Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, Washington, 1995. 515–523

    Google Scholar 

  128. Rai S, Neto W L, Miyasaka Y, et al. Logic synthesis meets machine learning: trading exactness for generalization. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2021. 1026–1031

    Google Scholar 

  129. Miyasaka Y, Zhang X, Yu M, et al. Logic synthesis for generalization and learning addition. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2021. 1032–1037

    Google Scholar 

  130. Cowen-Rivers A I, Lyu W, Tutunov R, et al. An empirical study of assumptions in Bayesian optimisation. 2020. ArXiv:2012.03826

    Google Scholar 

  131. Oh C, Bondesan R, Gavves E, et al. Batch Bayesian optimization on permutations using acquisition weighted kernels. 2021. ArXiv:2102.13382

    Google Scholar 

  132. Velic̆ković P, Cucurull G, Casanova A, et al. Graph attention networks. In: Proceedings of the 6th International Conference on Learning Representations, Vancouver, 2018. 1–12

    Google Scholar 

  133. Gu J, Jiang Z, Lin Y, et al. DREAMPlace 3.0: multi-electrostatics based robust VLSI placement with region constraints. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Virtual, 2020. 1–9

    Google Scholar 

  134. Lu J, Chen P, Chang C C, et al. ePlace: electrostatics-based placement using fast Fourier transform and Nesterov's method. ACM Trans Des Autom Electron Syst, 2015, 20: 1–34

    Article  Google Scholar 

  135. Cheng C K, Kahng A B, Kang I, et al. RePlAce: advancing solution quality and routability validation in global placement. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2018, 38: 1717–1730

    Article  Google Scholar 

  136. Lin Y, Pan D Z, Ren H, et al. DREAMPlace 2.0: open-source GPU-accelerated global and detailed placement for large-scale VLSI designs. In: Proceedings of China Semiconductor Technology International Conference, Shanghai, 2020. 1–4

    Google Scholar 

  137. Liao P, Liu S, Chen Z, et al. DREAMPlace 4.0: timing-driven global placement with momentum-based net weighting. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Virtual, 2022. 939–944

    Google Scholar 

  138. Xu Y, Zhang Y, Chu C. FastRoute 4.0: global router with efficient via minimization. In: Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, 2009. 576–581

    Google Scholar 

  139. Chen T-C, Chang Y-W. Modern floorplanning based on B*-tree and fast simulated annealing. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2006, 25: 637–650

    Article  Google Scholar 

  140. Xu Q, Chen S, Li B. Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning. Appl Soft Computing, 2016, 40: 150–160

    Article  Google Scholar 

  141. Cheng R, Yan J. On joint learning for solving placement and routing in chip design. In: Proceedings of Advances in Neural Information Processing Systems, 2021. 34: 16508–16519

    Google Scholar 

  142. Nam G J, Alpert C J, Villarrubia P, et al. The ISPD2005 placement contest and benchmark suite. In: Proceedings of the International Symposium on Physical Design, San Francisco, 2005. 216–220

    Google Scholar 

Download references

Acknowledgements

This work was partially supported by National Natural Science Foundation of China (Grant Nos. 61925208, 62222214, 62102399, U22A2028, U19B2019), Beijing Academy of Artificial Intelligence (BAAI), CAS Project for Young Scientists in Basic Research (Grant No. YSBR-029), and Youth Innovation Promotion Association CAS and Xplore Prize.

Author information

Authors and Affiliations

  1. State Key Lab of Processor, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Wenkai He, Xiaqing Li, Xinkai Song, Yifan Hao, Rui Zhang, Zidong Du & Yunji Chen

  2. University of Chinese Academy of Sciences, Beijing, 100049, China

    Wenkai He & Yunji Chen

  3. Cambricon Technologies, Beijing, 100191, China

    Wenkai He, Xinkai Song, Yifan Hao & Rui Zhang

Authors
  1. Wenkai He
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Xiaqing Li
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Xinkai Song
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Yifan Hao
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Rui Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Zidong Du
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Yunji Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yunji Chen.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

He, W., Li, X., Song, X. et al. Chip design with machine learning: a survey from algorithm perspective. Sci. China Inf. Sci. 66, 211101 (2023). https://doi.org/10.1007/s11432-022-3772-8

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11432-022-3772-8

Key words

Search

Navigation