Abstract
A bit-plane parallel architecture for a modified set partitioning in hierarchical trees (SPIHT) without lists algorithm, which uses breadth first search scheme, is proposed. The breadth first search scheme is suitable for very large scale integration (VLSI) implementation based on the analysis of SPIHT algorithm. The architecture has advantages of high parallelism, no intermediate buffer as a single tree is scanned. After field programmable gate arrays (FPGAs) synthesis and simulation, the throughput of the proposed architecture can reach 60 MSample/Sec. As the breadth first search scheme is very similar to that of SPIHT with lists, the quality of reconstructed images is almost the same with that of SPIHT with lists.
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Acknowledgments
This material is based upon work supported by the National Natural Science Foundation of China under Grant No. 60802076, the Fundamental Research Funds for the Central Universities under Grant No. JY10000903003, the Open Research Funds of State Key Lab. for novel software technology under Grant No.KFKT2010B28.The authors would like to thank the reviewers for their helpful comments and revisions.
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This material is based upon work supported by the National Natural Science Foundation of China under Grant No. 60802076, the Fundamental Research Funds for the Central Universities under Grant No. JY10000903003, the Open Research Funds of State Key Lab. for novel software technology under Grant No.KFKT2010B28.
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Liu, K., Lei, J. & Li, Y. A Novel VLSI Architecture of SPIHT Using Breadth First Search for Real-Time Applications. J Sign Process Syst 68, 113–125 (2012). https://doi.org/10.1007/s11265-011-0581-2
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DOI: https://doi.org/10.1007/s11265-011-0581-2