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Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

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Abstract

This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8 × 8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm 2 using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3 ~ 1/5 of the conventional DCT chips.

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Authors and Affiliations

  1. Department of Electronics Engineering and Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung, 824, Taiwan, Republic of China

    Shih-Chang Hsia, Chin-Feng Tsai, Szu-Hong Wang & King-Chu Hung

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  1. Shih-Chang Hsia
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  2. Chin-Feng Tsai
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  3. Szu-Hong Wang
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  4. King-Chu Hung
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Corresponding author

Correspondence to Shih-Chang Hsia.

Additional information

This work was supported by National Science Council, Republic of China, under Grant NSC92-2213-E-327-010.

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Hsia, SC., Tsai, CF., Wang, SH. et al. Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor. J Sign Process Syst Sign Image Video Technol 58, 161–172 (2010). https://doi.org/10.1007/s11265-009-0344-5

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  • DOI: https://doi.org/10.1007/s11265-009-0344-5

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