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Programmable CMOS CNN Cell Based on Floating-gate Inverter Unit

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Abstract

At present, the Cellular Neural Network (CNN) is a potential parallel structure able to perform image processing tasks in real-time when is effectively implemented in CMOS technology. The CNN silicon integration success is due mainly to the local connectivity of processing cells. In this work, an alternative design based on floating-gate MOS inverters is presented, which uses unipolar signals for solving binary tasks. The approach brings a fast response in a reduced silicon area, as shown through electrical simulations. A prototype cell in CMOS technology (AMI, 1.2 micron) was fabricated and tested for eight image processing tasks.

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References

  1. L. O. Chua and T. Roska, Cellular Neural Networks and Visual Computing, Cambridge University Press, UK, 2002.

    Book  Google Scholar 

  2. L. O. Chua, G. Gulak, E. Pierzchala, and A. Rodríguez-Vázquez, (Eds.), Cellular Neural Networks and Analog VLSI, Special Issue of Analog Integrated Circuits and Signal Processing, vol. 15, no. 3, Kluwer, USA, 1998.

  3. A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro, J. L. Huertas, and E. Sánchez-Sinencio, “Current-mode Techniques for the Implementation of Continuous and Discrete Time Cellular Neural Networks,” IEEE Trans. Circuits Syst. 1, vol. 40, no. 3, 1993, pp. 132–146, March.

    Google Scholar 

  4. Hanggi Martin, and Moschytz George S. (Eds.), Cellular Neural Networks Analysis, Design and Optimization, Kluwer, Ned, 2000.

  5. T. Shibata, and T. Ohmi, “A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations,” IEEE Trans. Electron Devices, vol. 39, no. 6, 1992, pp. 1444–1455, June.

    Article  Google Scholar 

  6. T. Shibata, and T. Ohmi, “Neuron MOS Binary-Logic Integrated Circuits—Part I: Design Fundamentals and Soft-Hardware-Logic Circuit Implementation,” IEEE Trans. Electron Devices, vol. 40, no. 3, 1993, pp. 570–576, March.

    Article  Google Scholar 

  7. K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment,” in IEEE International Solid-State Circuits Conference ISSCC95, session 19, San Francisco, 1995, pp. 320–322.

  8. K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clock-Controlled Neuron-MOS Logic Gates,” IEEE Trans. Circuits Syst.—II: Analog Digit. Signal Process., vol. 45, no. 4, 1998, pp. 518–522, April.

    Article  Google Scholar 

  9. M. Anguita, F. J. Pelayo, E. Ros, D. Palomar, and A. Prieto, “VLSI Implementations of CNNs for Image Processing and Vision Tasks: Single and Multiple Chip Approaches,” in Proceedings of the 4th IEEE International Workshop on Cellular Neural Networks and their Applications, IEEE Computer Soc. Press, 1996, June.

  10. T. Matsumoto, L. O. Chua, and H. Suzuki, “CNN cloning template: Shadow Detector,” IEEE Trans. Circuits Syst., vol. 37, 1990, pp. 1070–1073, August.

    Article  MathSciNet  MATH  Google Scholar 

  11. A. Passio and Kari Halonen, “A New Cell Output Nonlinearity for Dense Cellular Nonlinear Network Integration,” IEEE Trans. Circuits Syst., vol. 48, no. 3, 2001, pp. 272–280, March.

    Article  Google Scholar 

  12. J. A. Hegt, D. M. W. Leenaerts, and R. T. Wilmans, “A Novel Compact Architecture for a Programmable Full-range CNN in 0.5 μm CMOS Technology,” Fifth IEEE International Workshop on Cellular Neural Networks and their Applications, London, England 1998.

  13. S. Veni and B. Yamuna, “Hardware Implementation of CNN,” in Proceedings Int. Conference on Intelligent Sensing and Information Processing, 2005, pp. 320–325, 4–7 Jan.

  14. M. Leong, P. Vasconcelos, Jorge Fernandes, and Leonel Sousa, “A Programmable Cellular Neural Network Circuit,” in 17th Symposium on Integrated Circuit and Systems Design, SBCII 2004, pp. 186–191.

  15. M. Salerno, F. Sargeni, and V. Bonaiuto, “A 6 × 6 Cells Interconnection-Oriented programmable Chip for CNN”, Analog Integrated Circuits and Signal Processing, vol. 15, no. 3, 1998, pp. 239–250.

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Authors and Affiliations

  1. Mexico-State Autonomous University (UAEM-Ecatepec), Jose Revueltas 17 Col. Tierra Blanca, Ecatepec de Morelos, Estado de Mexico, Mexico, C.P. 55020

    Jesus E. Molinar-Solis

  2. Electrical Engineering Department, Center for Research and Advanced Studies (CINVESTAV-IPN), Av. Instituto Politecnico Nacional, No. 2508, Col. San Pedro Zacatenco, Del. G.A. Madero, C.P. 07360, Mexico, Mexico

    Felipe Gomez-Castaneda, Jose A. Moreno-Cadenas & Victor H. Ponce-Ponce

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  1. Jesus E. Molinar-Solis
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  2. Felipe Gomez-Castaneda
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  3. Jose A. Moreno-Cadenas
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  4. Victor H. Ponce-Ponce
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Correspondence to Jesus E. Molinar-Solis.

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Molinar-Solis, J.E., Gomez-Castaneda, F., Moreno-Cadenas, J.A. et al. Programmable CMOS CNN Cell Based on Floating-gate Inverter Unit. J VLSI Sign Process Syst Sign Im 49, 207–216 (2007). https://doi.org/10.1007/s11265-007-0056-7

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  • DOI: https://doi.org/10.1007/s11265-007-0056-7

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