Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture | Journal of Signal Processing Systems Skip to main content

Advertisement

Springer Nature Link
Log in

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. R.B. Lee and M.D. Smith, “Media Processing: A New Design Target,” IEEE Micro, vol. 16, 1996, pp. 6–9.

    Article  Google Scholar 

  2. K. Diefendorff and P.K. Dubey, “How Multimedia Workloads will Change Processor Design,” Computer, vol. 30, 1997, pp. 43–45.

    Article  Google Scholar 

  3. M. Maruyama, H. Nakahira, T. Araki, S. Sakiyama, Y. Kitao, K. Aono, and H. Yamada, “An Image Signal Multiprocessor on a Single Chip,” IEEE Journal of Solid-State Circuits, vol. 25, 1990, pp. 1476–1483.

    Article  Google Scholar 

  4. E.R. Fossum, “CMOS Image Sensors: Electronic Camera-on-a-Chip,” IEEE Transactions on Electron Devices, vol. 44, 1997, pp. 1689–1698.

    Article  Google Scholar 

  5. Y. Joo, J. Park, M. Thomas, K.S. Chung, M.A. Brooke, N.M. Jokerst, and D.S. Wills, “Smart CMOS Focal Plane Arrays: A Si CMOS Detector Array and Sigma-Delta Analog-to-Digital Converter Imaging System,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 5, 1999, pp. 296–305.

    Article  Google Scholar 

  6. T. Morris, E. Fletcher, C. Afghahi, S. Issa, K. Connolly, and J.-C. Korta, “A Column-Based Processing Array for High-Seed Digital Image Processing,” in Conference on Advanced Research in VLSI. Atlanta, GA, USA: IEEE Computer Society, 1999, pp. 42–56.

  7. R.W. Brodersen, “Why We Need a Custom Chip-in-a-Day Design Methodology,” http://www.mseconference.org/Talks/mse01_brodersen.pdf, International Conference on Microelectronic Systems Education, Mixed Signal & Fabrication Services Keynote Address, 2001.

  8. M.C. Herbordt and C.C. Weems, “An Empirical Study of Datapath, Memory Hierarchy, and Network in SIMD Array Architectures,” in International Conference on Computer Design: VLSI in Computers and Processors. Austin, TX, USA: IEEE Computer Society Press, 1995, pp. 546–551.

  9. M.C. Herbordt, A. Anand, O. Kidwai, R. Sam, and C.C. Weems, “Processor/memory/array Size Tradeoffs in the Design of SIMD Aays for a Spatially Mapped Workload,” in Fourth IEEE International Workshop on Computer Architecture for Machine Perception. Cambridge, MA, USA: IEEE Computer Society Press, 1997, pp. 12–21.

    Chapter  Google Scholar 

  10. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors 1999 Edition, 1999.

  11. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors 2002 Update, 2002.

  12. D. Yang, H. Tian, B. Fowler, X. Liu, and A. El Gamal, “Characterization of CMOS Image Sensors with Nyquist Rate Pixel Level ADC,” in Sensors, Cameras, and Applications for Digital Photography, vol. 3650. San Jose, CA, USA: SPIE—The International Society for Optical Engineering, 1999, pp. 52–62.

    Chapter  Google Scholar 

  13. P. Pirsch and H.-J. Stolberg, “VLSI Implementations of Image and Video Multimedia Processing Systems,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, 1998, pp. 878–891.

    Article  Google Scholar 

  14. A. Moini, Vision Chips, Boston: Kluwer Academic, 2000.

    Book  Google Scholar 

  15. E.-S. Eid and E.R. Fossum, “Real-Time Focal-Plane Array Image Processor,” in Automated Inspection and High-Speed Vision Architectures III, vol. 1197. Philadelphia, PA, USA: SPIE—The International Society for Optical Engineering, 1989, pp. 2– 12.

    Google Scholar 

  16. C. Mead, Analog VLSI and Neural Systems, Reading, Mass.: Addison-Wesley, 1989.

    Book  MATH  Google Scholar 

  17. J. Kramer and G. Indiveri, “Neuromorphic Vision Sensors and Preprocessors in System Applications,” in Advanced Focal Plane Arrays and Electronic Cameras II, vol. 3410. Zurich, Switzerland: SPIE—The International Society for Optical Engineering, 1998, pp. 134–146.

    Chapter  Google Scholar 

  18. L.O. Chua and L. Yang, “Cellular Neural Networks: Theory and Applications,” IEEE Transactions on Circuits and Systems, vol. 35, 1988, pp. 1257–1290.

    Article  MathSciNet  MATH  Google Scholar 

  19. S. Espejo, R. Dominguez-Castro, G. Linan, and A. Rodriguez-Vazquez, “A 64*64 CNN Universal Chip with Analog and Digital I/O,” in IEEE International Conference on Electronics, Circuits and Systems, vol. 1, 1998, pp. 203–206.

    Google Scholar 

  20. A. El Gamal, D. Yang, and B. Fowler, “Pixel Level Processing—Why, What, and How?” in Sensors, Cameras, and Applications for Digital Photography, vol. 3650. San Jose, CA, USA: SPIE—The International Society for Optical Engineering, 1999, pp. 2–13.

    Chapter  Google Scholar 

  21. R.F. Pierret, Semiconductor Device Fundamentals, Reading, Mass.: Addison-Wesley, 1996.

    Google Scholar 

  22. M.L. Riaziat, Introduction to High-Speed Electronics and Optoelectronics, New York: Wiley, 1996.

    MATH  Google Scholar 

  23. P. Bhattacharya, Semiconductor Optoelectronic Devices, Upper Saddle River, NJ: Prentice Hall, 1997.

    Google Scholar 

  24. A. Dupret, E. Belhaire, and J.-C. Rodier, “A High Current Large Bandwidth Photosensor on Standard CMOS Processes,” Advanced Focal Plane Arrays and Electronic Cameras, vol. 2950, 1996, pp. 36–44.

    Article  Google Scholar 

  25. T. Lule, S. Benthien, H. Keller, F. Mutze, P. Rieve, K. Seibel, and M. Sommer, “Sensitivity of CMOS Based Imagers and Scaling Perspectives,” IEEE Transactions on Electron Devices, vol. 47, 2000, pp. 2110–2122.

    Article  Google Scholar 

  26. M.L. Simpson, M.N. Ericson, G.E. Jellison, Jr., W.B. Dress, A.L. Wintenberg, and M. Bobrek, “Application Specific Spectral Response with CMOS Compatible Photodiodes,” IEEE Transactions on Electron Devices, vol. 46, 1999, pp. 905–913.

    Article  Google Scholar 

  27. S.K. Mendis, S.E. Kemeny, R.C. Gee, B. Pain, C.O. Staller, Q. Kim, and E.R. Fossum, “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid-State Circuits, vol. 32, 1997, pp. 187–197.

    Article  Google Scholar 

  28. E.R. Fossum, “Digital Camera System on a Chip,” IEEE Micro, vol. 18, 1998, pp. 8–15.

    Article  Google Scholar 

  29. M.W. Hauser, “Principles of Oversampling A/D Conversion,” Journal of the Audio Engineering Society, vol. 39, 1991, pp. 3–26.

    Google Scholar 

  30. J.G. Proakis, Digital communications, New York: McGraw-Hill, 1995.

    Google Scholar 

  31. J.C. Candy and G.C. Temes, “Institute of Electrical and Electronics Engineers, and IEEE Circuits and Systems Society,” Oversampling delta-sigma data converters: Theory, Design, and Simulation, Piscataway, NJ: IEEE Press, 1992.

    Google Scholar 

  32. M.W. Hauser and R.W. Brodersen, “Circuit and Technology Considerations for MOS Delta-sigma A/D Converters,” in International Symposium on Circuits and Systems, vol. 3. San Jose, CA, USA: IEEE, 1986, pp. 1310–1315.

    Google Scholar 

  33. M.W. Hauser and R.W. Brodersen, “Monolithic Decimation Filtering for Custom Delta-Sigma A/D Converters,” in International Conference on Acoustics, Speech, and Signal Processing, New York, NY, USA: ICASSP, vol. 4, 1988, pp. 2005–2008.

  34. M.W. Hauser, “Technology Scaling and Performance Limitations in Delta-Sigma Analog-Digital Converters,” International Symposium on Circuits and Systems, vol. 1, 1990, pp. 356–359.

    Article  Google Scholar 

  35. J. Nakamura, B. Pain, T. Nomoto, T. Nakamura, and E.R. Fossum, “On-Focal-Plane Signal Processing for Current-Mode Active Pixel Sensors,” IEEE Transactions on Electron Devices, vol. 44, 1997, pp. 1747–1758.

    Article  Google Scholar 

  36. L.G. McIlrath, “A Low-Power Low-Noise Ultrawide-Dynamic-Range CMOS Imager with Pixel-Parallel A/D Conversion,” IEEE Journal of Solid-State Circuits, vol. 36, 2001, pp. 846–853.

    Article  Google Scholar 

  37. Y. Perelman and R. Ginosar, “A Low-Light-Level Sensor for Medical Diagnostic Applications,” IEEE Journal of Solid-State Circuits, vol. 36, 2001, pp. 1553–1558.

    Article  Google Scholar 

  38. F. Paillet, D. Mercier, and T.M. Bernard, “Making the Most of 15 k Lambda2 Silicon Area for a Digital Retina PE,” in Advanced Focal Plane Arrays and Electronic Cameras II, Zurich, Switzerland: SPIE—The International Society for Optical Engineering, vol. 3410, 1998, pp. 158–167.

    Chapter  Google Scholar 

  39. R.L. Franch, J. Ji, and C.L. Chen, “A 640-ps, 0.25- mu m CMOS, 16* 64-b Three-Port Register File,” IEEE Journal of Solid-State Circuits, vol. 32, 1997, pp. 1288–1292.

    Article  Google Scholar 

  40. M. Nomura, M. Yamashina, K. Suzuki, M. Izumikawa, H. Igura, H. Abiko, K. Okabe, A. Ono, T. Nakayama, and H. Yamada, “A 500-MHz, 0.4- mu m CMOS, 32-word by 32-bit 3-port Register File,” IEEE 1995 Custom Integrated Circuits Conference. Santa Clara, CA, USA: IEEE, 1995, pp. 151–154.

    Chapter  Google Scholar 

  41. J.M. Mulder, N.T. Quach, and M.J. Flynn, “An Area Model for On-Chip Memories and its Application,” IEEE Journal of Solid-State Circuits, vol. 26, 1991, pp. 98–106.

    Article  Google Scholar 

  42. S. Rixner, W.J. Dally, B. Khailany, P. Mattson, U.J. Kapasi, and J.D. Owens, “Register Organization for Media Processing,” in Sixth International Symposium on High-Performance Computer Architecture, Touluse, France, 2000, pp. 375–386.

    Google Scholar 

  43. R.S. Bajwa, R.M. Owens, and M.J. Irwin, “Image Processing with the MGAP: A Cost Effective Solution,” in International Parallel Processing Symposium. Newport, CA, USA, 1993, pp. 439–443.

  44. R. Forchheimer and A. Astrom, “Near-Sensor Image Processing: A New Paradigm,” IEEE Transactions on Image Processing, vol. 3, 1994, pp. 736–746.

    Article  Google Scholar 

  45. A. Astrom, J.-E. Eklund, and R. Forchheimer, “Near-Sensor Image Processing—Theory and Practice,” in Advanced Focal Plane Arrays and Electronic Cameras, vol. 2950. Berlin, Germany: SPIE—The International Society for Optical Engineering, 1996, pp. 242–253.

    Chapter  Google Scholar 

  46. J.-E. Eklund, C. Svensson, and A. Astrom, “VLSI Implementation of a Focal Plane Image Processor—A Realization of the Near-Sensor Image Processing Concept,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, 1996, pp. 322–335.

    Article  Google Scholar 

  47. T. Komuro, I. Ishii, and M. Ishikawa, “General-Purpose Vision Chip Architecture for Real-Time Machine Vision,” Advanced Robotics, vol. 12, 1999, pp. 619–627.

    Article  Google Scholar 

  48. SIMPil Programming Environment, http://www.ece.gatech.edu/research/pica/curr_projects/civp/index.html.

  49. G. Heygster, “Rank Filters in Digital Image Processing,” Computer Graphics and Image Processing, vol. 19, 1982, pp. 148–164.

    Article  Google Scholar 

  50. M.J.T. Smith and A. Docef, A Study Guide for Digital Image Processing, Riverdale, GA: Scientific Publishers, 1997.

    Google Scholar 

  51. R.M. Haralick, S.R. Sternberg, and X. Zhuang, “Image Analysis Using Mathematical Morphology,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 9, 1987, pp. 532–550.

    Article  Google Scholar 

  52. International Telecommunications Union, http://www.itu.int/home/index.html.

  53. Texas Instruments Incorporated, http://dspvillage.ti.com/.

  54. W.H. Robinson, G.E. Triplett, and D.S. Wills, “Component Modeling for an Integrated Digital Pixel,” in 15th Annual Meeting IEEE Lasers and Electro-Optics Society (LEOS), Glasgow, Scotland: IEEE, vol. 1, 2002, pp. 37–38.

    Chapter  Google Scholar 

  55. A. Gentile, A. López-Lagunas, S.M. Chai, H.H. Cat, K.S. Chung, L. Codrescu, M. Deb, S.J. Ryu, M.F. Wolff, J.C. Eble, W.H. Robinson, T. Taha, D.S. Wills, M. Viera-Vera, W.E. Lugo-Beauchamp, L. Bustelo, R. Olivieri, J. Figueroa, and J.L. Cruz-Rivera, “Portable Multimedia Supercomputing,” Submitted to IEEE Transactions on Computers, vol. TC 114531, July 2001, pp. 43.

  56. H.-S. Wong, “Technology and Device Scaling Considerations for CMOS Imagers,” IEEE Transactions on Electron Devices, vol. 43, 1996, pp. 2131–2142.

    Article  Google Scholar 

  57. S.M. Chai, A. Gentile, and D.S. Wills, “Impact Of Power Density Limitation In Gigascale Integration For The SIMD Pixel Processor,” in 20th Anniversary Conference on Advanced Research in VLSI. Atlanta, GA, USA: IEEE Computer Society, 1999, pp. 57–71.

  58. A. Gentile, “Portable Multimedia Supercomputers: System Architecture Design and Evaluation,” in Electrical and Computer Engineering, Atlanta, GA: Georgia Institute of Technology, 2000, pp. 170.

    Google Scholar 

  59. A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, 1992, pp. 473–484.

    Article  Google Scholar 

  60. T.D. Burd and R.W. Brodersen, “Energy Efficient CMOS Microprocessor Design,” Twenty-Eighth Annual Hawaii International Conference on System Sciences, vol. 1, 1995, pp. 288– 297.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Portable Image Computation Architectures (PICA) Laboratory, Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, GA, 30332-0250, USA

    William H. Robinson & D. Scott Wills

Authors
  1. William H. Robinson
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. D. Scott Wills
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to William H. Robinson.

Additional information

Currently affiliated with the Department of Electrical Engineering and Computer Science at Vanderbilt University.

William H. Robinson is an Assistant Professor in the Department of Electrical Engineering and Computer Science at Vanderbilt University. He received his B.S. in electrical engineering from Florida Agricultural and Mechanical University in 1996 and his M.S. in electrical engineering from the Georgia Institute of Technology (Georgia Tech) in 1998. He received his Ph.D. in electrical and computer engineering from Georgia Tech in 2003. His research explores the system-level integration of computer architecture to understand the impact of technology on architecture design. Topics of interest include computer architecture design, VLSI design, image processing, and mixed-signal integration with applications to portable imaging devices, integrated sensor technology, and system-on-a-chip multimedia processing. He is a member of the IEEE and participates in the Computer Society, the Education Society, and the Lasers and Electro-Optics Society.

D. Scott Wills is a Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received his B.S. in Physics from Georgia Tech in 1983, and his S.M., E.E., and Sc.D. in Electrical Engineering and Computer Science from M.I.T. in 1985, 1987, and 1990, respectively. His research interests include short wire VLSI architectures, high throughput portable processing systems, architectural modeling for gigascale (GSI) technology, and high efficiency image processors. He is a senior member of the IEEE and the Computer Society and he is an associate editor of IEEE Transactions on Computers.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Robinson, W.H., Wills, D.S. Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture. J VLSI Sign Process Syst Sign Image Video Technol 41, 65–80 (2005). https://doi.org/10.1007/s11265-005-6251-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-005-6251-5

Keywords

Search

Navigation