Abstract
By ignoring some cell overlaps, global placement computes the best position for each cell to minimize the wirelength. It is an important stage in very large scale integration (VLSI) physical design, since circuit performance heavily depends on the placement results. In this paper, we propose an augmented Lagrangian method to solve the VLSI global placement problem. In the proposed method, a cautious dynamic density weight strategy is used to balance the wirelength objective and the density constraints, and an adaptive step size is used to obtain a trade-off between runtime and solution quality. The proposed method is tested on the IBM mixed-size benchmarks and the International Symposium on Physical Design 2006 placement contest benchmarks. Experimental results show that our global placement method outperforms the state-of-the-art placement approaches in terms of solution quality on most of the benchmarks.
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Acknowledgments
The authors would like to express their sincere appreciation to Prof. Yao-Wen Chang and his EDA Lab group, National Taiwan University, for providing the source code of NTUplace2 and the binary of NTUPlace3. Special thanks are also given to the editor and anonymous reviewers for their valuable suggestions and comments, which helped improving the quality of the manuscript greatly. This work was supported in part by the National Science Foundation of China (NSFC) under Grants 61170308 and 11326190, and in part by the National Key Basic Research Special Foundation (NKBRSF) of China under Grant 2011CB808000.
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A preliminary version of this paper was presented at the 13th International Conference on Parallel and Distributed Computing, Applications and Technologies in December 2012.
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Zhu, W., Chen, J. & Li, W. An augmented Lagrangian method for VLSI global placement. J Supercomput 69, 714–738 (2014). https://doi.org/10.1007/s11227-014-1113-1
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DOI: https://doi.org/10.1007/s11227-014-1113-1