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Automation of Test Program Synthesis for Processor Post-silicon Validation

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Abstract

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-to-detect faults remain unidentified by these autogenerated test programs. Also, these approaches have considered fault models which have low correlation with the gate-level fault models. This paper presents a greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor. Subsequently, the overall coverage is also improved. A selection probability is estimated from the testability properties of the processor components and assigned to every instruction to accelerate the test synthesis. The range of performance and scalability are comprehensively evaluated on a configurable MIPS processor and a full-fledged 7-stage pipeline SPARC V8 Leon3 soft processor using behavioral fault models. The efficacy of our approach was explained by demonstrating the correlation between behavioral faults and gate-level faults of MIPS processor for the proposed scheme. Experimental results show that improved coverages of 96.32% for the MIPS processor and 95.8% for the Leon3 processor are achieved in comparison with the conventional methods, which have about 90% coverage on the average.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, IIT Guwahati, Guwahati, India

    Vasudevan Madampu Suryasarman, Santosh Biswas & Aryabartta Sahu

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  1. Vasudevan Madampu Suryasarman
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  2. Santosh Biswas
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  3. Aryabartta Sahu
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Correspondence to Santosh Biswas.

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Responsible Editor: D. Gizopoulos

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Suryasarman, V.M., Biswas, S. & Sahu, A. Automation of Test Program Synthesis for Processor Post-silicon Validation. J Electron Test 34, 83–103 (2018). https://doi.org/10.1007/s10836-018-5709-x

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  • DOI: https://doi.org/10.1007/s10836-018-5709-x

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