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Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation

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Abstract

In this paper we address two key issues related to error-tolerability testing on image processing circuits, namely acceptable threshold determination and acceptability evaluation. A JPEG 2000 decoder is employed as a case study. We first carefully investigate the acceptability threshold values of images in terms of error rate and error significance. The investigation results show that appropriate threshold values should be determined depending on a number of factors, including size (resolution), brightness, contrast and frequency of test images as well as human subjectiveness. Based on the determined threshold values we propose an equivalent error rate transformation technique to help test engineers easily and quickly examine the acceptability of a circuit under test. We also carry out hardware implementation of the proposed technique. The implementation results show that the hardware area overhead with respect to a commercial JPEG decoder design is only 2.24 %. To validate the proposed technique, 13,860 erroneous color images produced by faulty JPEG 2000 decoders as well as 450 erroneous benchmark images are employed. The experimental results show that the proposed technique is as effective as the exhaustive test method. Moreover, our technique requires much less test time and storage space compared with the exhaustive test method. The achievable reduction ratio in test time and storage space is more than 99 %.

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References

  1. Rivers JA, Kudva P (2009) Reliability challenges and system performance at the architecture level. IEEE Design & Test of Computers 26(6):62–73

    Article  Google Scholar 

  2. Breuer MA, Gupta SK, Mak TM (2004) Defect and error-tolerance in the presence of massive numbers of defects. IEEE Design & Test of Computers 21(3):216–227

    Article  Google Scholar 

  3. I. Chong and A. Ortega (2005) Hardware testing for error tolerant multimedia compression based on linear transforms. Proc. Int’l. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 523–531

  4. C.-L. Hsu, Y.-S. Huang and T.-H. Liu (2008) SSD-based testing scheme for error tolerance analysis in H.264/AVC encoder. Proc. Int’l. Conf. on Communications, Circuits and Systems, pp. 684–688

  5. H. Chung and A. Ortega (2005) Analysis and testing for error tolerant motion estimation. Proc. Int’l. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 514–522

  6. Breuer MA, Zhu H (2008) An illustrated methodology for analysis of error-tolerance. IEEE Design & Test of Computers 25(2):168–177

    Article  Google Scholar 

  7. A. M. Eltawil and F. J. Kurdahi (2005) Improving effective yield through error tolerant system design. Proc. IEEE Conf. on Electronics, Circuits and Systems, pp. 1–4

  8. G. V. Varatkar and N. R. Shanbhag (2006) Energy-efficient motion estimation using error-tolerance. Proc. Int’l Symp. on Low Power Electronics and Design, pp. 113–118

  9. Pan S-J, Cheng K-T (2007) A framework for system reliability analysis considering both system error tolerance and component test quality. Proc. Design Automation and Test in, Europe, pp 1581–1586

    Google Scholar 

  10. H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Cheng and C.-W. Wu (2010) An error tolerance scheme for 3D CMOS imagers. Proc. Design Automation Conf., pp. 917–922

  11. Hsu C-L, Huang YS, Chang MD, Huang HY (2011) Design of an error-tolerance scheme for discrete wavelet transform in JPEG 2000 encoder. IEEE Trans Comput 60(5):628–638

    Article  MathSciNet  Google Scholar 

  12. Y. Fang, H. Li, and X. Li (2011) A fault criticality evaluation framework of digital systems for error tolerant video applications. Proc. Asian Test Symp., pp. 329–334

  13. Pan Z, Breuer MA (2007) Estimating error-rate in defective logic using signature analysis. IEEE Trans Comput 56(5):650–661

    Article  MathSciNet  Google Scholar 

  14. S. Shahidi and S. K. Gupta (2006) Estimating error rate during self-test via one’s counting. Proc. Int’l. Test Conf., pp. 1–9

  15. Z. Pan and M. A. Breuer (2008) Ones counting based error-rate estimation for multiple output circuits. Proc. Int’l. Workshop on Design and Test of Nano Devices, pp. 59–62

  16. Hsieh T-Y, Lee K-J, Breuer MA (2008) An error-rate based test methodology to support error-tolerance. IEEE Trans Reliab 57(1):204–214

    Article  Google Scholar 

  17. Dinesh Jayaraman, Anish Mittal, Anush K. Moorthy and Alan C. Bovik (2012) Objective Quality Assessment of Multiply Distorted Images, Proceedings of Asilomar Conference on Signals, Systems and Computers

  18. Daubechies I, Sweldens W (1998) Factoring wavelet transforms into lifting steps. The Journal of Fourier Analysis and Applications 4(3):247–269

    Article  MATH  MathSciNet  Google Scholar 

  19. S. T. Welstead (1999) Fractal and Wavelet Image Compression Techniques, SPIE Publication

  20. http://www.cast-inc.com/ip-cores/images/jpeg-d/

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Acknowledgments

This work was supported in part by the Ministry of Science and Technology of Taiwan under Contract Number NSC 101-2221-E-110-096-MY2 and MOST 103-2221-E-110-077-MY3.

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Authors and Affiliations

  1. EE Department, National Sun Yat-sen University, Kaohsiung City, Taiwan

    Tong-Yu Hsieh, Yi-Han Peng & Kuan-Hsien Li

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  1. Tong-Yu Hsieh
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  2. Yi-Han Peng
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  3. Kuan-Hsien Li
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Correspondence to Tong-Yu Hsieh.

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Responsible Editor: J.-L. Huang

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Hsieh, TY., Peng, YH. & Li, KH. Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation. J Electron Test 30, 687–699 (2014). https://doi.org/10.1007/s10836-014-5488-y

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  • DOI: https://doi.org/10.1007/s10836-014-5488-y

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