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Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow

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Abstract

Model-order reduction (MOR) is a typical approach to speed up the post-layout verification simulation step in circuit design. This paper studies the benefits of using circuit partitioning in a complete MOR flow. First, an efficient reduction algorithm package comprising of partitioning, reduction, and realization parts is presented. The reduction flow is then discussed using theoretical analysis and simulations from an array of 65-nm technology node interconnect circuits. It is shown that the reduction efficiency and computational costs quickly worsen with increased circuit size when using a direct projection-based MOR approach. In contrast, by using partitioning, the MOR can retain the scalability of the reduction problem, being computationally lighter and more efficient even with larger circuits. In addition, using partitioning may improve the robustness of the MOR flow in cases with circuits with many ports or sensitive verification simulations.

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Acknowledgments

This work was partially funded by the Finnish national Graduate School in Electronics, Telecommunications and Automation. Financial support from the Nokia Foundation is acknowledged.

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Authors and Affiliations

  1. Department of Radio Science and Engineering, Aalto University School of Electrical Engineering, P.O.Box 13000, FI-00076, Aalto, Finland

    Pekka Miettinen, Mikko Honkala & Martti Valtonen

  2. AWR-APLAC Corporation, Lars Sonckin kaari 10, FI-02600, Espoo, Finland

    Janne Roos

Authors
  1. Pekka Miettinen
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  2. Mikko Honkala
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  3. Janne Roos
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  4. Martti Valtonen
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Correspondence to Pekka Miettinen.

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Responsible Editor: V. Champac

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Miettinen, P., Honkala, M., Roos, J. et al. Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow. J Electron Test 30, 271–285 (2014). https://doi.org/10.1007/s10836-014-5451-y

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  • DOI: https://doi.org/10.1007/s10836-014-5451-y

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