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A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis

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Abstract

This paper reports a case study on the automatic layout generation and transient fault injection analysis of a Phase-Locked Loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. Experiences were performed in the PLL in order to evaluate the sensibility against transient faults. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18 μm). Results reveal the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

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References

  1. Ammari A (2006) Durcissement et analyse de sûreté de citcuits integrés décrits en langage de haut niveau. Thesis proposition, Institut National Polytechnique de Grenoble, France

  2. Cadence Design Systems (2006) Cadence Design Systems homepage. http://www.cadence.com

  3. Lazzari C, Domingues C, Güntzel J, Reis R (2003) A new macro-cell generation strategy for three metal layer CMOS technologies. VLSI-Soc, Nice, pp 193–197

    Google Scholar 

  4. Lyons G, Wu G, Mellissinos T, Cable J (1999) A high performance rad hard 2–3 GHz integer N CMOS phase lock loop. Radiation effects data workshop 1999. IEEE, Piscataway, pp 41–45

    Google Scholar 

  5. Martínez I, Delatte P, Flandre D (2000) Characterization, simulation and modeling of PLL under irradiation using HDL-A. BMAS 2000. 2000 IEEE International Behavioral Modeling and Simulation Conference. IEEE, Piscataway, pp 57–61

    Google Scholar 

  6. Messenger G (1982) Collection of charge on junction nodes from ion tracks. IEEE Trans Nucl Sci 29:2024–2031

    Article  Google Scholar 

  7. Pan D, Li HW, Wilamowski BM (2003) A radiation-hard phase-locked loop. ISIE’03. 2003 IEEE international symposium on industrial electronics, vol 2. IEEE, Piscataway, pp 901–906

    Google Scholar 

  8. Saleh S (2005) Méthodes de simulation des erreurs transitoires à plusiers niveaux d’abstraction. Thesis Dissertation, Institut National Polytechnique de Grenoble, France

  9. Toifl T, Moreira P (1999) A radiation-hard 80 MHz phase locked loop for clock and data recovery. In: Proceedings of the 1999 IEEE international symposium on circuits and systems, ISCAS ’99, vol. 2. IEEE, Piscataway, pp 524–527

    Chapter  Google Scholar 

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Authors and Affiliations

  1. PGMICRO, UFRGS, Porto Alegre, Brazil

    Cristiano Lazzari

  2. PGMICRO/PPGC, Instituto de Informática, UFRGS, Porto Alegre, Brazil

    Ricardo A. L. Reis

  3. TIMA Laboratory, INPG, Grenoble, France

    Lorena Anghel

Authors
  1. Cristiano Lazzari
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  2. Ricardo A. L. Reis
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  3. Lorena Anghel
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Corresponding author

Correspondence to Cristiano Lazzari.

Additional information

Responsible Editor: M. Lubaszewski

Supported by CAPES Brazilian Research Agency.

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Lazzari, C., Reis, R.A.L. & Anghel, L. A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. J Electron Test 23, 625–633 (2007). https://doi.org/10.1007/s10836-007-5055-x

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  • DOI: https://doi.org/10.1007/s10836-007-5055-x

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