Abstract
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs’ dependability, but it increases the time for running the hardened application, as well as the memory occupation. In this paper we propose a method that eliminates the memory overhead, by exploiting a new approach to instruction hardening and control flow checking. The proposed method hardens an application online during its execution, without the need for introducing any change in its source code, and is non-intrusive, since it does not require any modification in the main processor’s architecture. The method has been tested with two widely used architectures: a microcontroller and a RISC processor, and proven to be suitable for hardening SoCs against transient faults and also for detecting permanent faults.
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References
Aho A, Sethi R, Ullman J (1986) Compilers: principles, techniques and tools. Addison-Wesley, Reading, MA
Alkhalifa Z, Nair VSS, Krishnamurthy N, Abraham JA (1999) Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans Parallel Distrib Syst 10(6):627–641 (Jun)
Austin TM (2000) DIVA: a dynamic approach to microprocessor verification. Journal of Instruction Level Parallelism 2(May)1–6 http://www.jilp.org/vol2
Beck F, Mattos JCB, Wagner FR, Carro L (2003) CACO-PS: a general purpose cycle-accurate configurable power-simulator. In: Proceedings of the 16th Brazilian symposium on integrated circuits and systems design (SBCCI 2003), September 2003
Bernardi P, Bolzani LMV, Rebaudengo M, Sonza Reorda M, Vargas FL, Violante M (2006) A new hybrid fault detection technique for Systems-on-a-Chip. IEEE Trans Comput 55(2):185–198 (Feb)
Cheynet P, Nicolescu B, Velazco R, Rebaudengo M, Sonza Reorda M, Violante M (2000) Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors. IEEE Trans Nucl Sci 47(6 part 3):2231–2236 (Dec)
Civera P, Macchiarulo L, Rebaudengo M, Sonza Reorda M, Violante M (2001) Exploiting circuit emulation for fast hardness evaluation. IEEE Trans Nucl Sci 48(6):2210–2216 (Dec)
Eto A, Hidaka M, Okuyama Y, Kimura K, Hosono M (1998) Impact of neutron flux on soft errors in MOS memories. In: Proceedings of the IEEE international electronic devices meeting (IEDM), IEEE Computer Society, Los Alamitos, CA, pp 367–380
Goloubeva O, Rebaudengo M, Sonza Reorda M, Violante M (2003) Soft-error detection using control flow assertions. In: Proceedings of the 18th IEEE international symposium on defect and fault tolerance in VLSI systems—DFT 2003, November 2003, pp 581–588
Huang KH, Abraham JA (1984) Algorithm-based fault tolerance for matrix operations. IEEE Trans Comput 33:518–528 (Dec)
Lisbôa CAL, Carro L, Sonza Reorda M, Violante M (2006) Online hardening of programs against SEUs and SETs. In: Proceedings of the 21st IEEE international symposium on defect and fault tolerance in VLSI systems—DFT 2006, IEEE Computer Society, Los Alamitos, CA, October 2006, pp 280–288
Mahmood A, McCluskey EJ (1988) Concurrent error detection using watchdog processors—a survey. IEEE Trans Comput 37(2):160–174 (Feb)
Mahmood A, Lu DJ, McCluskey EJ (1983) Concurrent fault detection using a watchdog processor and assertions. In Proceedings of the IEEE international test conference 1983 (ITC ’83), pp. 622–628
Namjoo M (1983) CERBERUS-16: an architecture for a general purpose watchdog processor. In: Proceedings of the 13th international symposium on fault-tolerant computing (FTCS-13), pp 216–219
Namjoo M, McCluskey EJ (1982) Watchdog processors and capability checking. In: Proceedings of the 12th international symposium on fault-tolerant computing (FTCS-12), pp 245–248
Oh N, Mitra S, McCluskey EJ (2002) ED4I: error detection by diverse data and duplicated instructions. IEEE Trans Comput 51(2):180–199 (Feb)
Oh N, Shirvani PP, McCluskey EJ (2002) Control flow Checking by Software Signatures. IEEE Trans Reliab 51(2):111–112 (Mar)
Ohlsson J, Rimen M (1995) Implicit signature checking. In: Digest of papers of the 25th international symposium on fault-tolerant computing (FTCS-25), pp 218–227
Quach N (2000) High availability and reliability in the Itanium processor. IEEE MICRO 20(5):61–69 (Sep–Oct)
Schillaci M, Sonza Reorda M, Violante M (2006) A new approach to cope with single event upsets in processor-based systems. In: Proceedings of the 7th IEEE Latin–American test workshop—LATW 2006, March 2006, pp 145–150
Schuette MA, Shen JP (1987) Processor control flow monitoring using signatured instruction streams. IEEE Trans Comput 36(3):264–276 (Mar)
Stolicny C (2006) ITC 2005 panels. IEEE Des Test Comput 20(5):164–166 (Mar–Apr)
Vijaykrishnan N (2005) Soft-errors: is the concern for soft errors overblown? In: Proceedings of the IEEE international test conference 2005 (ITC 2005), November 2005 (2 pages)
Weaver C, Gebara FF, Austin T, Brown R (2002) Remora: a dynamic self-tuning processor. University of Michigan CSE Technical Report CSE-TR-460-02, July 2002. University of Michigan, MI, USA
Wilken K, Shen JP (1990) Continuous signature monitoring: low-cost concurrent detection of processor control errors. IEEE Trans Comput-Aided Des Integr Circuits Syst 9(6):629–641 (Jun)
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Rhod, E.L., Lisbôa, C.A.L., Carro, L. et al. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. J Electron Test 24, 45–56 (2008). https://doi.org/10.1007/s10836-007-5018-2
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DOI: https://doi.org/10.1007/s10836-007-5018-2