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Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA

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Abstract

Assessment of power consumption is very important for an efficient digital integrated circuit design. Dynamic power in digital programmable CMOS-based processors depends on the switching activity. Specifically in its subcomponents like FIR filter, power consumption can be directly related to the node switching activity. Minimization of power consumption can be done by reducing the transitions or dissimilarities in filter coefficients. Evolutionary algorithms (EAs) have been found to be very effective for optimized FIR filter design because of nonlinear, nondifferentiable, multimodal and nonconvex nature of the associated optimization problem. However, all the existing evolutionary optimization-based design techniques aim at meeting the frequency domain specifications without concentrating on minimizing power consumption. In the present work, a novel EA, i.e., hybrid artificial bee colony algorithm, has been proposed and further applied for FIR filter design. The filter design task aims at satisfying the dual objectives of meeting the desired frequency domain specifications and power minimization.

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References

  1. J.I. Ababneh, M.H. Bataineh, Linear phase FIR filter design using particle swarm optimization and genetic algorithms. Digit. Signal Process. 18(4), 657–668 (2008)

    Article  Google Scholar 

  2. M. Aktan, U. Cini, G. Dundar, Design of digital filters for low power applications by reducing the Hamming distance of the filter coefficients using mean field annealing algorithm, in IEEE Conference on Signal Processing and Communications Applications, pp. 646–648 (2004)

  3. T. Arslan, A.P. Erdogan, D.H. Horrocks, Low power design for DSP: methodologies and techniques. Microelectron. J. 27(8), 731–744 (1996)

    Article  Google Scholar 

  4. M. Azarmehr, M. Ahmadi, Low-power finite impulse response (FIR) filter design using two-dimensional logarithmic number system (2DLNS) representations. Circuits Syst. Signal Process. 31(6), 2075–2091 (2012)

    Article  MathSciNet  Google Scholar 

  5. T.S. Bindiya, E. Elias, Modified meta-heuristic algorithms for the optimal design of multiplier-less non-uniform channel filters. Circuits Syst. Signal Process. 33(3), 815–837 (2014)

    Article  Google Scholar 

  6. K.C. Chang, C.H. Lin, C.W. Liu, Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier, in IEEE International Symposium on VLSI Design, Automation and Test, VLSI-DAT, pp. 1–4 (2014)

  7. A.T. Erdogan, T. Arslan, On the low-power implementation of FIR filtering structures on single multiplier DSPs. IEEE Trans. Circuits Syst. II Analog Digital Signal Process. 49(3), 223–229 (2002)

    Article  Google Scholar 

  8. C.W. Fong, H. Asmuni, W.S. Lam, B. McCollum, P. McMullan, A novel hybrid swarm based approach for curriculum based time tabling problem, in IEEE Congress on Evolutionary Computation, CEC, pp. 545–550 (2014)

  9. O. Gustafsson, L. Wanhammar, Design of linear-phase FIR filters with minimum Hamming distance, in IEEE Nordic Signal Processing Symposium, INSPS, pp. 4–7 (2002)

  10. R.L. Haupt, S.E. Haupt, Practical genetic algorithms, 2nd edn. (Wiley, London, 2004)

    MATH  Google Scholar 

  11. S. Hong, S.S. Chin, S. Kim, W. Hwang, Multiplier architecture power consumption characterization for low-power DSP applications, in 9th International Conference on Electronics, Circuits and Systems, 2002, vol. 2, pp. 741–744 (2002)

  12. F. Kanf, L. Junjie, H. Li, Z. Ma, Q. Xu, An improved artificial bee colony algorithm, in IEEE 2nd International Workshop on Intelligent Systems and Application, pp. 174–177 (2010)

  13. F. Kang, J. Li, Q. Xu, Structural Inverse analysis by hybrid simplex artificial bee colony algorithms. Comput Struct 87(13), 861–870 (2009)

    Article  Google Scholar 

  14. N. Karaboga, B. Cetinkaya, Design of digital FIR filters using differential evolution algorithm. Circuits Syst. Signal Process. 25(5), 649–660 (2006)

    Article  MathSciNet  MATH  Google Scholar 

  15. D. Karaboga, A. Bahriye, A powerful and efficient algorithm for numerical function optimization: artificial bee colony algorithm. J. Glob. Optim. 39(3), 459–471 (2007)

    Article  MathSciNet  MATH  Google Scholar 

  16. D. Karaboga, B. Akay, A comparative study of artificial bee colony algorithm. Appl. Math. Comput. 21(4), 108–132 (2009)

    MathSciNet  MATH  Google Scholar 

  17. A. Kavita, K. Sasi, Minimizing switching activities through reordering algorithm for efficient power management. J. Sci. Ind. Res. 73, 421–426 (2014)

    Google Scholar 

  18. S. Kockanat, N. Karaboga, A novel 2D-ABC adaptive filter algorithm: a comparative study. Digital Signal Process. 40, 140–153 (2015)

    Article  MathSciNet  Google Scholar 

  19. D.J. Krusienski, W.K. Jenkins, A modified particle swarm optimization algorithm for adaptive filtering, in IEEE International Symposium on Circuits and Systems, ISCAS, pp. 137–140 (2006)

  20. B. Luitel, K. Venayagamoorthy, Differential evolution particle swarm optimization for digital filter design, in IEEE Congress on Evolutionary Computation, pp. 3954–3961 (2008)

  21. M. Mahendele, S.D. Sherlekar, G. Venkatesh, Coefficient optimization for low power realization of FIR filters, in IEEE Workshop on VLSI Signal Processing, IWVSP, pp. 352–361(1995)

  22. M.N. Mahesh, M. Mahendele, Low power realization of residue number system based FIR filters, in IEEE Thirteenth International Conference on VLSI Design, ICVLSI, pp. 30–33 (2000)

  23. K. Masselos, S. Theoharis, P. Merakos, T. Stouraitis, C.E. Goutis, Memory accesses reordering for interconnect power reduction in sum-of-products computations. IEEE Trans. Signal Process. 50(11), 2889–2899 (2002)

    Article  Google Scholar 

  24. M. Mehendale, S.D. Sherlekar, G. Venkatesh, Algorithmic and architectural transformations for low power realization of FIR filters, in Eleventh IEEE International Conference on VLSI Design, pp. 12–17 (1998)

  25. P.K. Merakos, K. Masseslos, O. Koufopaviou, S. Nikolaidis, C.E. Goutis, A novel transformation for reduction of switching activity in FIR filters implementation, in IEEE International Conference on Digital Signal Processing, ICDSP, pp. 2653–2656 (1997)

  26. M. Najjarzadeh, A. Ayatollahi, FIR digital filters design: particle swarm optimization utilizing LMS and minimax strategies, in IEEE International Symposium on Signal Processing and Information Technology, ISSPIT, pp. 129–132 (2008)

  27. N.F. Najm, Transitions density: a new measure of activity in digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2), 310–323 (1993)

    Article  Google Scholar 

  28. J.A. Nelder, A simplex method for function minimization. Comput. J. 7(4), 308–313 (1965)

    Article  MathSciNet  MATH  Google Scholar 

  29. M. Nemani, F.N. Najm, Towards a high-level power estimation capability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6), 588–598 (1996)

    Article  Google Scholar 

  30. S.H. Ou, K.C. Chang, C.W. Liu, An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. Integr. VLSI J. 48, 230–238 (2015)

    Article  Google Scholar 

  31. P. Puri, S. Ghosh, A hybrid optimization approach for PI controller tuning based on gain and phase margin specifications. Swarm Evol. Comput. 8, 69–78 (2013)

    Article  Google Scholar 

  32. J.G. Rahmeier, A.G. Luz, C.C. Eduardo, Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm, in IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS, pp. 33–36 (2013)

  33. S.K. Saha, R. Kar, D. Mandal, S.P. Ghosal, Seeker optimization algorithm: application to the design of linear phase FIR filter. IET Signal Process. 6(8), 763–771 (2012)

    Article  MathSciNet  Google Scholar 

  34. S.K. Saha, R. Dutta, R. Choudhury, R. Kar, D. Mandal, S.P. Ghosal, Efficient and accurate optimal linear phase fir filter design using opposition-based harmony search algorithm. Sci. World J. 2013, 1–16 (2013)

  35. S.K. Saha, S.P. Ghoshal, R. Kar, D. Mandal, Cat swarm optimization algorithm for optimal linear phase FIR filter design. ISA Trans. 52(6), 781–794 (2013)

    Article  Google Scholar 

  36. N. Sankararayya, K. Roy, D. Bhattacharya, Algorithms for low power and high speed FIR filter realization using differential coefficients. IEEE Trans. Circuits Syst. II Analog Digital Signal Process. 44(6), 488–497 (1997)

    Article  Google Scholar 

  37. Z. Shao, B. Xio, C. Xue, Q. Zhuge, H.-M.S. Edwin, Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Trans. Des. Autom. Electron. Syst. 11(1), 165–185 (2006)

    Article  Google Scholar 

  38. C.L. Su, C.Y. Tsui, A.M. Despain, Low power architecture design and compilation techniques for high-performance processors, in IEEE Compcon Spring’94. Digest of Papers, pp. 489–498 (1994)

  39. H. Takano, I. Nobuhiro, Y. Takeshi, Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction, U.S. Patent 5,790,874, 4 Aug(1998)

  40. W. Tang, T. Shen, Optimal design of FRM-based FIR filters by using hybrid Taguchi genetic algorithm, in Proceedings of the 1st International Conference on Green Circuits and Systems, ICGCS, pp. 392–397 (2010)

  41. R. Velegalati, K. Shah, J.P. Kaps, Glitch detection in hardware implementations on FPGAs using delay based sampling techniques, in IEEE European Micro Conference on Digital System Design, DSD, pp. 947–954 (2013)

  42. J. Xie, J. He, G. Tan, FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. Microelectron. J. 41(6), 365–370 (2010)

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical Engineering, NIT, Raipur, 492010, India

    Atul Kumar Dwivedi, Subhojit Ghosh & Narendra D. Londhe

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  1. Atul Kumar Dwivedi
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  2. Subhojit Ghosh
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  3. Narendra D. Londhe
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Correspondence to Subhojit Ghosh.

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Dwivedi, A.K., Ghosh, S. & Londhe, N.D. Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA. Circuits Syst Signal Process 36, 156–180 (2017). https://doi.org/10.1007/s00034-016-0297-4

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