Abstract
Low-power techniques are proposed for the wireless three-dimensional Network-on-Chips (wireless 3-D NoCs), in which routers on the same chip are connected with metal wires while those on the different chips are connected wirelessly using the inductive-coupling. For saving power consumption of the vertical link, the clock and power supplies to the transmitter are stopped when their utilizations are between a specified range. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold. In order to keep performance, on-demand activation is used in this paper. As long as flit comes, the dormant data transmitter or the whole vertical link will be activated immediately without any judgement. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 23.4%-29.3%, while the performance overhead is less than 2.4%.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H., McCaule, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J.P., Webb, C.: Die Stacking (3D) Microarchitecture. In: Proceedings of the International Symposium on Microarchitecture (MICRO 2006), pp. 469–479 (December 2006)
Kumagai, K., Yang, C., Goto, S., Ikenaga, T., Mabuchi, Y., Yoshida, K.: System-in-Silicon Architecture and its application to an H.264/AVC motion estimation fort 1080HDTV. In: Proceedings of the International Solid-State Circuits Conference (ISSCC 2006), pp. 430–431 (February 2006)
Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.: Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design and Test of Computers 22(6), 498–510 (2005)
Miura, N., Ishikuro, H., Sakurai, T., Kuroda, T.: A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. In: Proceedings of the International Solid-State Circuits Conference (ISSCC 2007), pp. 358–359 (February 2007)
Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T., Amano, H.: A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs. In: Proceedings of the International Symposium on Networks-on-Chip (NOCS 2011), pp. 49–56 (May 2007)
Soteriou, V., Peh, L.-S.: Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks. IEEE Transactions on Parallel and Distributed Systems 18(3), 393–408 (2007)
Kim, E., Yum, K., Link, G., Vijaykrishnan, N., Kandemir, M., Irwin, M., Yousif, M., Das, C.: Energy optimization techniques in cluster interconnects. In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003, pp. 459–464 (August 2003)
Lee, S.E., Bagherzadeh, N.: A variable frequency link for a power-aware network-on-chip (NoC). Integr. VLSI J. 42, 479–485 (2009)
Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H., Amano, H.: Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(4), 520–533 (2011)
Gebhardt, D., Stevens, K.: Power reduction through physical placement of asynchronous routers. In: 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009, p. 92 (May 2009)
Kim, C., Burger, D., Keckler, S.W.: An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches. In: Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2002), pp. 211–222 (October 2002)
Agarwal, N., Peh, L.-S., Jha, N.: Garnet: A Detailed Interconnection Network Model inside a Full-system Simulation Framework. Technical Report CE-P08-001. Princeton University (2008)
Jin, H., Frumkin, M., Yan, J.: The OpenMP Implementation of NAS Parallel Benchmarks and Its Performane. In: NAS Technical Report NAS-1999 (October 1999)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Zhang, H., Matsutani, H., Take, Y., Kuroda, T., Amano, H. (2012). Vertical Link On/Off Control Methods for Wireless 3-D NoCs. In: Herkersdorf, A., Römer, K., Brinkschulte, U. (eds) Architecture of Computing Systems – ARCS 2012. ARCS 2012. Lecture Notes in Computer Science, vol 7179. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28293-5_18
Download citation
DOI: https://doi.org/10.1007/978-3-642-28293-5_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-28292-8
Online ISBN: 978-3-642-28293-5
eBook Packages: Computer ScienceComputer Science (R0)