Abstract
In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model the timing and functional specifications of our interface. The FDR model checker and its tau-priority model were used to prove that the properties of the configured interface are within the properties of targeted communication protocols.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
AbuKharmeh, S., Eder, K., May, D.: Formal analysis of a programmable performance-critical processor communication interface. In: Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (2010), http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2001286
Altera Corporate: Stratix GX FPGA, Family Datasheet (2004)
American National Standards Institute: Standards for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (CSMA-CD) - Standards 802.3. John Wiley & Sons, Inc., New York (1985)
ARM Ltd.: AMBATMSpecification Revision 2 (1999)
Böhm, P., Melham, T.: A refinement approach to design and verification of on-chip communication protocols. In: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design (2008)
Electronics Industries Association: EIA standard RS-232-C interface between data terminal equipment and data communication equipment employing serial data interchange. Tech. rep., Electronics Industries Association (1969)
Formal Systems: Failures-Divergence Refinement FDR2, User Manual, 2.91 edn. (May 2010)
Freescale Semiconductor Inc: MPC5121e serial peripheral interface (SPI). online (2009)
Hoare, C.A.R.: Communicating Sequential Processes. Prentice Hall International, Englewood Cliffs (2004)
Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In: Proceedings of the 39th Annual Design Automation Conference, DAC 2002, vol. (39), pp. 343–348. ACM, New York (2002)
International Organization for Standardization: ISO 11898-1:2003 - Road vehicles – Controller area network (CAN) – Part 1: Data link layer and physical signalling. Tech. rep., ISO (2003)
Kaizhi, Y.: Validating system requirements by functional decomposition and dynamic analysis. In: Proceedings of the 11th International Conference on Software Engineering, ICSE 1989, pp. 188–196. ACM, New York (1989)
Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12(8), 203–215 (2007)
May, D., Muller, H., Hedinger, P., Dixon, A., Owen, R., Richards, N.: XS1 Ports: use and specification. XMOS Ltd., 1.02 edn. (November 2008)
Microchip Inc: PIC16F87X Microcontrollers Datasheet (2001)
Müffke, F.: A better way to design communication protocols. Ph.D. thesis, University of Bristol (May 2004)
Open Microprocessor Systems Initiative: OMI 324: PI-Bus. Tech. rep., OMI (1994)
Ouaknine, J.: Discrete analysis of continuous behaviour in real-time concurrent systems. Ph.D. thesis, Oxford University (2001)
Philips Semiconductors: The I2C-Bus specification. Tech. rep., Philips (2000)
Roscoe, A.W.: Understanding Concurrent Systems, 1st edn. Texts in Computer Science. Springer, Heidelberg (2010)
Schneider, S.: Concurrent and Real Time Systems: The CSP Approach. John Wiley & Sons, Inc., New York (1999)
Seidel, K.: Case study: Specification and refinement of the PI-Bus. In: Naftalin, M., Bertrán, M., Denvir, T. (eds.) FME 1994. LNCS, vol. 873, pp. 532–546. Springer, Heidelberg (1994)
Spars, J., Furber, S.: Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, Boston (2001)
Tretmans, J.: A Formal Approach to Conformance Testing. Ph.D. thesis, University of Twente, Enschede (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Abu Kharmeh, S., Eder, K., May, D. (2011). A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface. In: Fahrenberg, U., Tripakis, S. (eds) Formal Modeling and Analysis of Timed Systems. FORMATS 2011. Lecture Notes in Computer Science, vol 6919. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24310-3_23
Download citation
DOI: https://doi.org/10.1007/978-3-642-24310-3_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24309-7
Online ISBN: 978-3-642-24310-3
eBook Packages: Computer ScienceComputer Science (R0)