Abstract
Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is imperative to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to consider the correlation of these variations to increase the accuracy of the performance computation. In this paper, we present an efficient method for performance evaluation of asynchronous circuits considering inter and intra-die process variation. The proposed method includes both statistical static timing analysis (SSTA) and statistical Timed Petri-Net based simulation. Template-based asynchronous circuit has been modeled using Variant-Timed Petri-Net. Based on this model, the proposed SSTA calculates the probability density function of the delay of global critical cycle. The efficiency for the proposed SSTA is obtained from a technique that is derived from the principal component analysis (PCA) method. This technique simplifies the computation of mean, variance and covariance values of a set of correlated random variables. In order to consider spatial correlation in the Petri-Net based simulation, we also include a correlation coefficient to the proposed Variant-Timed Petri-Net which is obtained from partitioning the circuit. We also present a simulation tool of Variant-Timed Petri-Net and the results of the experiments are compared with Monte-Carlo simulation-based method.
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Raji, M., Ghavami, B., Zarandi, H.R., Pedram, H. (2010). Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_5
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DOI: https://doi.org/10.1007/978-3-642-11802-9_5
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