Abstract
Leakage currents represent emergent design parameters in nanometer CMOS technologies. Leakage mechanisms interact with each other at device level (through device geometry and doping profile), at gate level (through intra-cell node voltage) and at circuit level (through inter-cell node voltages). In this paper, the impact of loading effect in the standby power consumption is evaluated in relation to the gate oxide leakage magnitude and the routing resistivity. Simulation results, considering a 32nm technology node, have demonstrated an increase of up to 15% in the total circuit leakage dissipation due to the loading effect influenced by wire resistance.
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References
Semiconductor Industry Association, International Roadmap for Semiconductor (2006), http://public.itrs.net
Roy, K., et al.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-submicron CMOS Circuits. Proc. IEEE 91(2), 305–327 (2003)
Agarwal, et al.: Leakage Power Analysis and Reduction: Models, Estimation and Tools. IEE Proceedings – Computers and Digital Techniques 152(3), 353–368 (2005)
Narendra, S., et al.: Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18um CMOS. IEEE Journal of Solid-State Circuits 39(3), 501–510 (2004)
Cheng, Z., et al.: Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks. In: Proc. Int. Symposium Low Power Electronics and Design, pp. 239–244 (1998)
Rao, R.M., et al.: Efficient Techniques for Gate Leakage Estimation. In: Proc. Int. Symposium Low Power Electronics and Design, pp. 100–103 (2003)
Ono, et al.: A 100nm Node CMOS Technology for Practical SOC Application Requirement. Tech. Digest of IEDM, pp. 511–514 (2001)
Gusev, E., et al.: Ultrathin High-k Gate Stacks for Advanced CMOS Devices. Tech. Digest of IEDM, pp. 451–454 (2001)
Butzen, P.F., et al.: Simple and Accurate Method for Fast Static Current Estimation in CMOS Complex Gates with Interaction of Leakage Mechanisms. In: Proceedings Great Lakes Symposium on VLSI, pp. 407–410 (2008)
Mukhopadhyay, S., Bhunia, S., Roy, K.: Modeling and Analysis of Loading Effect on Leakage of Nanoscaled Bulk-CMOS Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8), 1486–1495 (2006)
Rastogi, W., Chen, S.: On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuit Based on Newton-Raphson Method. In: Proc. of Design Automation Conf., pp. 712–715 (2007)
Horowitz, M.A., Ho, R., Mai, K.: The Future of Wires. Proceedings of the IEEE 89(4), 490–504 (2001)
Nangate FreePDK45 Generic Open Cell Library (2009), http://www.si2.org/openeda.si2.org/projects/nangatelib
Zhao, W., Cao, Y.: New generation of Predictive Technology Model for sub-45nm early design exploration. IEEE Transactions on Electron Devices 53(11), 2816–2823 (2006)
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Butzen, P.F., Reis, A.I., Ribas, R.P. (2010). Routing Resistance Influence in Loading Effect on Leakage Analysis. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_36
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DOI: https://doi.org/10.1007/978-3-642-11802-9_36
Publisher Name: Springer, Berlin, Heidelberg
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