Abstract
In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.
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Sepúlveda, R., Montiel, O., Olivas, J., Castillo, O. (2009). Methodology to Test and Validate a VHDL Inference Engine of a Type-2 FIS, through the Xilinx System Generator. In: Castillo, O., Pedrycz, W., Kacprzyk, J. (eds) Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. Studies in Computational Intelligence, vol 257. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04514-1_17
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DOI: https://doi.org/10.1007/978-3-642-04514-1_17
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