Abstract
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal transition time difference. For conventional dynamic power estimation, deterministic models of the time difference are assumed. We deal with nondeterministic models considering variations, because variations such as process variations cause the input arrival time variations. As a result of the time variations, power estimation error may increase. In our analysis and experiments, firstly impact of the time variations on the power consumption is analytically modeled. Then, it is demonstrated that certain types of bus coding techniques suppress the impact.
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Muroyama, M., Ishihara, T., Yasuura, H. (2009). Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_7
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DOI: https://doi.org/10.1007/978-3-540-95948-9_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
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