Abstract
The paper addresses the design partitioning into multiple FPGA devices. The industrial experience shows that the designers were never satisfied by the full automatic partitioning: as the design size grows, it takes longer CPU times and produces poor results. The present paper proposes an algorithm which may be integrated into the mixed interactive manual/automatic partitioning framework. The hierarchy nodes of the design are selected one by one and assigned to a defined set of FPGA devices. The automatic partitioning algorithm is called to split a big node among the selected subset of devices taking into account previous assignments to these devices. Experimental results show that the proposed approach works well for big industrial circuits.
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References
Behrens, D., Harbich, K., Barke, E.: Hierarchical Partitioning. In: Proc. Int. Conf. on Computed-Aided Design, pp. 470–477 (1996)
Bui, T.N., Heigham, C., Jones, C., Leighton, T.: Improving the Performance of the Kernigan-Lin and Simulated Annealing graph bisection algorithms. In: Proc. 26th Design Automation Conference, pp. 775–778 (1989)
Chou, N.-C., Liu, L.-T., Cheng, C.-K., Dai, W.-L., Lindelof, R.: Circuit Partitioning for Huge Logic Emulation Systems. In: Proc. 31st Design Automation Conference, pp. 244–249 (1994)
Cheng, C.-K., Wei, Y.-C.A.: An improved two-way partitioning algorithm with stable performance. IEEE Trans. on Computer-Aided Design of ICs and Systems 10/12, 1502–1511 (1991)
Eikerling, H.-J., Rosenstiel, W.: Automatic Structuring and Optimization of Hierarchical Designs. In: Proc. Euro-DAC with Euro-VHDL, pp. 134–139 (1996)
Fang, W.-J., Wu, A.C.-H.: A Hierarchical Functional Structuring and Partitioning Approach for Multiple-FPGA Implementations. In: Proc. Int. Conf on Computed-Aided Design, pp. 638–643 (1996)
Fang, W.-J., Wu, A.C.-H.: Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. In: Proc. 34-th Design Automation Conference, pp. 518–521 (1997)
Garbers, J., Promel, H.J., Steger, A.: Finding Clusters in VLSI circuits. In: Proc. Int. Conf. on Computed-Aided Design, pp. 520–523 (1990)
Krupnova, H., Abbara, A., Saucier, G.: A Hierarchy-Driven FPGA Partitioning Method. In: Proc. 34-th Design Automation Conference, pp. 522–524 (1997)
Krupnova, H., Saucier, G.: Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. In: Proc. Int. Conf. Design, Automation and Test in Europe, pp. 587–594 (1999)
Ng, T.K., Oldfield, J., Pitchumani, V.: Improvements of A Min-Cut Partition Algorithm. In: Proc. Int. Conf. on Computed-Aided Design, pp. 470–473 (1987)
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© 1999 Springer-Verlag Berlin Heidelberg
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Krupnova, H., Saucier, G. (1999). Hierarchical Interactive Approach to Partition Large Designs into FPGAs. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_11
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DOI: https://doi.org/10.1007/978-3-540-48302-1_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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