Simulation Semantics for Min-Max DEVS Models

Abstract

The representation of timing, a key element in modeling hardware behavior, is realized in hardware description languages including ADLIB-SABLE, Verilog, and VHDL, through delay constructs. In the real world, precise values for delays are very difficult, if not impossible, to obtain with certainty. The reasons include variations in the manufacturing process, temperature, voltage, and other environmental parameters. Consequently, simulations that employ precise delay values are susceptible to inaccurate results. This paper proposes an extension to the classical DEVS by introducing Min-Max delays. In the augmented formalism, termed Min-Max DEVS, the state of a hardware model may, in some time interval, become unknown and is represented by the symbol, φ. The occurrence of φ implies greater accuracy of the results, not lack of information. Min-Max DEVS offers a unique advantage, namely, the execution of a single simulation pass utilizing Min-Max delays is equivalent to multiple simulation passes, each corresponding to a set of precise delay values selected from the interval. This, in turn, poses a key challenge – efficient execution of the Min-Max DEVS simulator.