Abstract
This paper presents a set of experiments in formal modelling and verification of a deadlock avoidance algorithm of an Automatic Train Supervision System (ATS). The algorithm is modelled and verified using four formal environment, namely UMC, Promela/SPIN, NuSMV, and mCRL2. The experience gained in this multiple modelling/verification experiments is described. We show that the algorithm design, structured as a set of concurrent activities cooperating through a shared memory, can be replicated in all the formal frameworks taken into consideration with relative effort. In addition, we highlight specific peculiarities of the various tools and languages, which emerged along our experience.
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Notes
- 1.
All the verification experiments have been conducted on a Mac Pro (late 2013) workstation with Quad-core 3,7Ghz Intel Xeon E5, 64 GB RAM running OS X 10.11 (El Capitan). All the models referred in this paper can be retrieved from the URL http://fmt.isti.cnr.it/WEBPAPER/ISOLA2016data.zip.
- 2.
Each configuration corresponding to a point in Fig. 3, with associated verification time, is available at http://fmt.isti.cnr.it/WEBPAPER/ISOLA2016data.zip.
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Mazzanti, F., Ferrari, A., Spagnolo, G.O. (2016). Experiments in Formal Modelling of a Deadlock Avoidance Algorithm for a CBTC System. In: Margaria, T., Steffen, B. (eds) Leveraging Applications of Formal Methods, Verification and Validation: Discussion, Dissemination, Applications. ISoLA 2016. Lecture Notes in Computer Science(), vol 9953. Springer, Cham. https://doi.org/10.1007/978-3-319-47169-3_22
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