Abstract
The emerging RISC-V ecosystem has the potential to improve the speed, fidelity, and quality of hardware/software co-design R &D activities. However, the suitability of the RISC-V ecosystem for co-design targeting HPC use cases is not yet well understood. In this paper, we examine the performance of several HPC benchmark workloads running on simulated open-source hardware RISC-V cores running under the FireSim FPGA-accelerated simulation tool. To provide a realistic and reproducible HPC software stack, we port the Spack package manager to RISC-V and use it to build our workloads. Our key finding is that each of the RISC-V cores evaluated is capable of running complex HPC workloads executing for long durations under simulation, with simulation rates of approximately 1/50th real-time. Additionally we provide a baseline set of performance results that can be compared against in future studies. Our results highlight the readiness of the RISC-V ecosystem for performing open co-design activities for HPC. We expect performance to improve as co-design activities targeting RISC-V ramp up and the RISC-V community makes further contributions to this space.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Amid, A., Asanovic, K., Baum, A., Bradbury, A., Brewer, T., et al.: RISC-V ‘V’ Vector Extension (2021). https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf
Amid, A., et al.: Chipyard: integrated design, simulation, and implementation framework for custom SoCs. IEEE Micro 40(4), 10–21 (2020). https://doi.org/10.1109/MM.2020.2996616
Arekapudi, S., Xie, D.: Ocelot: open source vector unit. In: RISC-V Summit 2022, San Jose, California (2022)
Asanović, K., et al.: The rocket chip generator. Technical report UCB/EECS-2016-17, EECS Department, University of California, Berkeley (2016). http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html
Bachrach, J., et al.: Chisel: constructing hardware in a scala embedded language. In: Proceedings of the 49th Annual Design Automation Conference, DAC 2012, pp. 1216–1225. Association for Computing Machinery, New York (2012). https://doi.org/10.1145/2228360.2228584
Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011). https://doi.org/10.1145/2024716.2024718
Dongarra, J., Heroux, M.: Toward a new metric for ranking high performance computing systems. Technical report SAND2013-4744, Sandia National Laboratories, NM, USA (2013)
Dongarra, J., Luszczek, P., Heroux, M.: HPCG technical specification. Technical report SAND2013-8752, Sandia National Laboratories, NM, USA (2013)
Dörflinger, A., et al.: A comparative survey of open-source application-class RISC-V processor implementations. In: Proceedings of the 18th ACM International Conference on Computing Frontiers, CF 2021, pp. 12–20. Association for Computing Machinery, New York (2021). https://doi.org/10.1145/3457388.3458657
Frenkel, C., Indiveri, G.: ReckOn: a 28nm sub-mm2 task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65, pp. 1–3. IEEE (2022)
Frenkel, C., Lefebvre, M., Legat, J.D., Bol, D.: A 0.086-mm\(^2\) 12.7-pJ/SOP 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm CMOS. IEEE Trans. Biomed. Circ. Syst. 13(1), 145–158 (2018)
Gamblin, T., et al.: The Spack package manager: bringing order to HPC software chaos. In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2015 (2015). https://doi.org/10.1145/2807591.2807623
Hsieh, M., Pedretti, K., Meng, J., Coskun, A., Levenhagen, M., Rodrigues, A.: SST + gem5 = a scalable simulation infrastructure for high performance computing. In: Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques, pp. 196–201 (2012)
Karandikar, S., et al.: FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud. In: Proceedings of the 45th Annual International Symposium on Computer Architecture, ISCA 2018, Piscataway, NJ, USA, pp. 29–42. IEEE Press (2018). https://doi.org/10.1109/ISCA.2018.00014
Kretz, M.: Extending C++ for explicit data-parallel programming via SIMD vector types. Doctoral thesis, Universitätsbibliothek Johann Christian Senckenberg (2015). https://doi.org/10.13140/RG.2.1.2355.4323
Lowe-Power, J., et al.: The gem5 simulator: version 20.0+ (2020). https://doi.org/10.48550/arXiv.2007.03152
McCalpin, J.D.: Memory bandwidth and machine balance in current high performance computers. IEEE Comput. Soc. Tech. Comm. Comput. Archit. (TCCA) Newsl. 2, 19–25 (1995). https://www.cs.virginia.edu/mccalpin/papers/balance/
Pedretti, K., et al.: Chronicles of Astra: challenges and lessons from the first petascale arm supercomputer. In: SC 2020: International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1–14. IEEE (2020)
Rodrigues, A.F., et al.: The structural simulation toolkit. SIGMETRICS Perform. Eval. Rev. 38(4), 37–42 (2011). https://doi.org/10.1145/1964218.1964225
Rutishauser, G., Hunziker, R., Di Mauro, A., Bian, S., Benini, L., Magno, M.: ColibriES: a milliwatts RISC-V based embedded system leveraging neuromorphic and neural networks hardware accelerators for low-latency closed-loop control applications. arXiv preprint arXiv:2302.07957 (2023)
Saad, Y.: Iterative Methods for Sparse Linear Systems. SIAM (2003)
Sato, M., Kodama, Y., Tsuji, M., Odajima, T.: Co-design and system for the supercomputer “Fugaku". IEEE Micro 42(2), 26–34 (2022). https://doi.org/10.1109/MM.2021.3136882
Stephens, N., et al.: The ARM scalable vector extension. IEEE Micro 37(2), 26–39 (2017). https://doi.org/10.1109/MM.2017.35
Ta, T., Cheng, L., Batten, C.: Simulating multi-core RISC-V systems in gem5. In: Workshop on Computer Architecture Research with RISC-V (2018)
Wang, J., et al.: RISC-V toolchain and agile development based open-source neuromorphic processor. arXiv preprint arXiv:2210.00562 (2022)
Yousefzadeh, A., et al.: SENeCA: scalable energy-efficient neuromorphic computer architecture. In: 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 371–374. IEEE (2022)
Zaruba, F., Benini, L.: The cost of application-class processing: energy and performance analysis of a Linux-ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(11), 2629–2640 (2019). https://doi.org/10.1109/TVLSI.2019.2926114
Zelensky, A., Alepko, A., Dubovskov, V., Kuptsov, V.: Heterogeneous neuromorphic processor based on RISC-V architecture for real-time robotics tasks. In: Artificial Intelligence and Machine Learning in Defense Applications II, vol. 11543, pp. 94–101. SPIE (2020)
Zhang, S., Wright, A., Bourgeat, T., Arvind, A.: Composable building blocks to open up processor design. In: 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 68–81 (2018). https://doi.org/10.1109/MICRO.2018.00015
Zhao, J., Korpan, B., Gonzalez, A., Asanovic, K.: SonicBOOM: the 3rd generation Berkeley out-of-order machine. In: Fourth Workshop on Computer Architecture Research with RISC-V (2020). https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf
Acknowledgments
This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.
This article has been authored by an employee of National Technology & Engineering Solutions of Sandia, LLC under Contract No. DE-NA0003525 with the U.S. Department of Energy (DOE). The employee owns all right, title and interest in and to the article and is solely responsible for its contents. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce the published form of this article or allow others to do so, for United States Government purposes. The DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan https://www.energy.gov/downloads/doe-public-access-plan.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Berger-Vergiat, L. et al. (2023). Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware. In: Bienz, A., Weiland, M., Baboulin, M., Kruse, C. (eds) High Performance Computing. ISC High Performance 2023. Lecture Notes in Computer Science, vol 13999. Springer, Cham. https://doi.org/10.1007/978-3-031-40843-4_40
Download citation
DOI: https://doi.org/10.1007/978-3-031-40843-4_40
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-40842-7
Online ISBN: 978-3-031-40843-4
eBook Packages: Computer ScienceComputer Science (R0)