Abstract
This paper is concerned with practicable solutions to a dynamic circuit reconfiguration problem: how to perform runtime routing of data between blocks of circuitry. The solutions use a ‘virtual circuitry’ approach based on the notion of Swappable Logic Units (SLUs). They involve a continuum of three types of routing model in which communication channels are made available using some form of extra configured logic supplied by an operating system. These models involve trade-offs between flexibility, speed and cell count; however, all stop short of any impractical attempt at arbitrary routing at run time. The models also illustrate a blurring of traditional notions of ‘hardware’ and ‘software’, at a point where circuitry meets instruction sequences.
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References
Brebner, “Relating Routing Graphs and Two-dimensional Grids”, Proc. VLSI Algorithms and Architectures, North Holland Publ., 1984, pp.221–231.
Brebner and Gray, “Use of reconfigurability in variable-length code detection at video rates”, Proc. 5th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 975, 1995, pp.429–438.
Brebner, “A Virtual Hardware Operating System for the Xilinx XC6200”, Proc. 6th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 1142, 1996, pp.327–336.
Brebner, “The Swappable Logic Unit: a Paradigm for Virtual Hardware”, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997, pp.77–86.
Burns, Donlin, Hogg, Singh and de Wit, “A Dynamic Reconfiguration Run Time System”, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IPSEE Computer Society Press 1997, pp.66–75.
Donlin, “A Dynamically Self-Modifying Processor Architecture and its Application to Active Networking”, Working Paper, Department of Computer Science, University of Edinburgh, September 1997.
Eggers, Lysa ht, Dick and McGregor, “Fast Reconfigurable Crossbar Switching in FPGAs”, broc. 6th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 1142, 1996, pp.297–306.
Jones, “The Ultimate RISC”, Computer Architecture News 16 3, June 1988, pp.48–55.
Mead and Conway, Introduction to VLSI Systems, Reading:Addison-Wesley 1980.
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© 1998 Springer-Verlag Berlin Heidelberg
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Brebner, G., Donlin, A. (1998). Runtime reconfigurable routing. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_668
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DOI: https://doi.org/10.1007/3-540-64359-1_668
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