Abstract
The future advanced technologies of devices will enable to implement some number of processors into a single chip. We call such a chip the multiprocessor-chip. In such a multiprocessor-chip, architectural trade-off is completely different from current bus connected multiprocessors. In order to emulate such future multiprocessors, a reconfigurable testbed multiprocessor ATTEMPT-1 is proposed. By using programmable devices (CPLDs and FPGAs) in the core of the system, various parameters of the cache and bus system are selectable. Since the each core of controller is described in the HDL (Hardware Description Language) and implemented on CPLD, cache protocols and bus protocols can be changed just by rewriting description on the state transitions. By using high speed FPGAs in the data path, enough high speed (25MHz clock) is kept in spite of its flexibilty.
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© 1996 Springer-Verlag Berlin Heidelberg
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Inoue, K., Kisuki, T., Okuno, M., Shimizu, E., Terasawa, T., Amano, H. (1996). Attempt-1: A reconfigurable multiprocessor testbed. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_21
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DOI: https://doi.org/10.1007/3-540-61730-2_21
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