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Barrier semantics in very weak memory

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PARLE '93 Parallel Architectures and Languages Europe (PARLE 1993)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 694))

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Abstract

The fundamental model of memory requires each read to an address to return the most recent value written to the same address. This model becomes a consistency requirement for parallel shared memory machines, and is taken as a necessary property for correct algorithm execution. In Distributed Shared Memory (DSM) systems the presence of processor memory caches means that the processors may develop historical and therefore different views of the distributed memory. The paper examines the relationship between synchronisation and consistency, proposes that synchronisation should enforce consistency, and examines the consequences using barriers as an example. A typical shared memory MIMD program is shown to execute correctly without normal consistency, and the experiment suggests that the relationship between synchronisation and consistency bears further investigation.

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References

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Author information

Authors and Affiliations

  1. Dept. of Comp. Sci. and Comp. Eng., La Trobe University, Australia

    Arnold Pears

  2. High Performance Computing, CSIRO, DIT, Australia

    Rhys Francis

Authors
  1. Arnold Pears
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  2. Rhys Francis
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Editor information

Arndt Bode Mike Reeve Gottfried Wolf

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© 1993 Springer-Verlag Berlin Heidelberg

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Pears, A., Francis, R. (1993). Barrier semantics in very weak memory. In: Bode, A., Reeve, M., Wolf, G. (eds) PARLE '93 Parallel Architectures and Languages Europe. PARLE 1993. Lecture Notes in Computer Science, vol 694. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56891-3_70

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  • DOI: https://doi.org/10.1007/3-540-56891-3_70

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56891-9

  • Online ISBN: 978-3-540-47779-2

  • eBook Packages: Springer Book Archive

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