Abstract
System Generator is a high level design tool well suited to creating custom DSP data paths in FPGAs. While providing a high level abstraction of an FPGA circuit, it can be used to build designs comparable to hand crafted implementations in terms of area and performance. In this paper we use a MAC-based FIR filter design example to demonstrate the interplay between mathematical abstraction and hardware-centric considerations enabled by System Generator. We demonstrate how an algorithm can be efficiently mapped onto FPGA resources and present the hardware results of several System Generator FIR filter implementations.
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© 2002 Springer-Verlag Berlin Heidelberg
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Hwang, J., Ballagh, J. (2002). Building Custom FIR Filters Using System Generator. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_117
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DOI: https://doi.org/10.1007/3-540-46117-5_117
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