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Verifying a Simple Pipelined Microprocessor Using Maude

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Recent Trends in Algebraic Development Techniques (WADT 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2267))

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Abstract

We consider the verification of a simple pipelined microprocessor in Maude, by implementing an equational theoretical model of systems. Maude is an equationally-based language, with an efficient term rewriting implementation, and effective meta-level tools. Microprocessors and other systems are modelled as iterated maps operating in time over some state-set, and are related by means of data and abstraction maps, and correctness is reduced to state exploration by the choice of an appropriate initialization function, ensuring/enforcing consistency of the initial state.

This work is supported by UK EPSRC grants GR/N15955 and GR/M82202. The author is grateful to the referees for their insights, and their helpful comments and suggestions.

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References

  1. G Birtwistle and B Graham. Verifying SECD in HOL. In J Staunstrup, editor, Formal Methods for VLSI Design, pages 129–177. North-Holland, 1990.

    Google Scholar 

  2. J Burch. Techniques for verifying superscalar microprocessors. In Design Automation Conference, 1996.

    Google Scholar 

  3. J Burch and D Dill. Automatic Verification of pipelined microprocessor control. In D Dill, editor, Proceedings of the 6th International Conference, CAV’94: Computer-Aided Verification, pages 68–80. Lecture Notes in Computer Science 818, Springer-Verlag, 1994.

    Google Scholar 

  4. M Clavel, F Durán, S Eker, P Lincoln, N MartfOliet, J Meseguer, and J Quesada. Maude: specification and programming in rewriting logic. Technical report, Computer Science Laboratory, SRI International, 1999.

    Google Scholar 

  5. A Cohn. A proof of correctness of the Viper microprocessor: the first levels. In G Birtwistle and P A Subrahmanyam, editors, VLSI specification, Verification and Synthesis, pages 27–72. Kluwer Academic Publishers, 1987.

    Google Scholar 

  6. B Cook, J Launchbury, and J Matthews. Specifying superscalar microprocessors in Hawk. In M Sheeran, editor, Workshop on Formal Methods for Hardware (Marstrand, Sweden), 1998.

    Google Scholar 

  7. D Cyrluk, J Rushby, and M Srivas. Systematic formal Verification of interpreters. In IEEE International Conference on Formal Engineering Methods (ICFEM’97, pages 140–149, 1997.

    Google Scholar 

  8. A C J Fox. Algebraic Representation of Advanced Microprocessors. PhD thesis, Department of Computer Science, University of Wales Swansea, 1998.

    Google Scholar 

  9. A C J Fox. Algebraic Techniques for Verifying Microprocessors in HOL. Computer Laboratory Report 512, University of Cambridge, 2001.

    Google Scholar 

  10. A C J Fox and N A Harman. An algebraic model of correctness for superscalar microprocessors. In Formal Methods in Computer-Aided Design, pages 346–361. Lecture Notes in Computer Science 1166, Springer-Verlag, 1996.

    Chapter  Google Scholar 

  11. A C J Fox and N A Harman. Algebraic models of correctness for microprocessors. Formal Aspects of Computer Science, 12:298–312, 2000.

    Article  MATH  Google Scholar 

  12. A C J Fox and N A Harman. Algebraic models of superscalar microprocessor implementations: A case study. In B Möller and J V Tucker, editors, Prospects for Hardware Foundations, pages 138–183. Lecture Notes in Computer Science 1546, Springer-Verlag, 1998.

    Chapter  Google Scholar 

  13. A C J Fox and N A Harman. Algebraic models of temporal abstraction for initialised iterated state systems: An abstract pipelined case study. Technical Report CSR 21-98, University of Wales Swansea, 1998, submitted to the Journal of Algebraic and Logic Programming.

    Google Scholar 

  14. B Graham. The SECD Microprocessor: a Verification Case Study. Kluwer, 1992.

    Google Scholar 

  15. M J C Gordon and T F Melham. Introduction to HOL. Cambridge University Press, 1993.

    Google Scholar 

  16. N A Harman. Correctness and Verification of hardware systems using Maude. Technical Report Computer Science Report, University of Wales Swansea, 2000.

    Google Scholar 

  17. N A Harman and J V Tucker. The formal specification of a digital correlator I: Abstract user specification. In K McEvoy and J V Tucker, editors, Theoretical Foundations for VLSI Design, pages 161–262. Cambridge University Press Tracts in Theoretical Computer Science 10, 1990.

    Google Scholar 

  18. N A Harman and J V Tucker. Algebraic models of microprocessors: Architecture and organisation. Acta Informatica, 33:421–456, 1996.

    Article  MATH  MathSciNet  Google Scholar 

  19. N A Harman and J V Tucker. Algebraic models of microprocessors: the Verification of a simple computer. In V Stavridou, editor, Proceedings of the 1995 IMA Conference on Mathematics for Dependable Systems. Oxford University Press, 1997.

    Google Scholar 

  20. J L Hennessy and D A Patterson. Computer Architecture: A Quantative Approach. Morgan Kaufman, 1996.

    Google Scholar 

  21. R Hosabettu, M Srivas, and G Gopalakrishnan. Decomposing the proof of correctness of pipelined microprocessors. In A J Hu and M Y Vardi, editors, Computer Aided Verification: 10th International Conference, pages 122–134. Springer-Verlag, Lecture Notes in Computer Science 1427, 1998.

    Chapter  Google Scholar 

  22. J Sawada W A Hunt. Processor Verification with precise exceptions and speculative execution. In A J Hu and M Y Vardi, editors, Computer Aided Verification: 10th International Conference, pages 135–147. Springer-Verlag, Lecture Notes in Computer Science 1427, 1998.

    Chapter  Google Scholar 

  23. R B Jones, J U Skakkebæk, and D Dill. Reducing manual abstraction in formal Verification of out-of-order execution. In G Gopalakrishnan and P Windley, editors, Formal Methods in Computer-Aided Design, FMCAD 98, pages 2–17. Springer-Verlag, Lecture Notes in Computer Science 1522, 1998.

    Chapter  Google Scholar 

  24. J U Skakkebæk, R B Jones, and D Dill. Formal Verification of out-of-order execution using incremental ushing. In A J Hu and M Y Vardi, editors, Computer Aided Verification: 10th International Conference, pages 98–109. Springer-Verlag, Lecture Notes in Computer Science 1427, 1998.

    Chapter  Google Scholar 

  25. S Krstic, B Cook, J Launchbury, and J Matthews. A correctness proof of a speculative, superscalar, out-of-order, renaming microarchitecture. Technical report, Oregon Graduate Institute, 1998.

    Google Scholar 

  26. F Durán M Clavel, S Eker, and J Meseguer. Building equational proving tools by reection in rewriting logic. In K Futatsugi, A T Nakagawa and T Tamai, editors, CAFE: An Industrial-Strength Algebraic Formal Method, pages 1–31, Elsevier, 2000.

    Google Scholar 

  27. K Meinke and J V Tucker. Universal algebra. In T S E Maibaum S Abramsky, D Gabbay, editor, Handbook of Logic in Computer Science, pages 189–411. Oxford University Press, 1992.

    Google Scholar 

  28. S Miller and M Srivas. Formal Verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods. In Proceedings of WIFT 95, Boca Raton, 1995.

    Google Scholar 

  29. S Owre, J Rushby, N Shankar, and M Srivas. A tutorial on using PVS. In Proceedings of TPCD 94, pages 258–279. Lecture Notes in Computer Science 901, Springer-Verlag, 1994.

    Google Scholar 

  30. M Srivas, H Rueβ, and D Cyrluk. Hardware Verification using PVS. In T Kropf, editor, Formal Hardware Verification, pages 156–205. Springer-Verlag, Lecture Notes in Computer Science 1287, 1997.

    Google Scholar 

  31. K Stephenson. An Algebraic Approach to Syntax, Semantics and Compilation. PhD thesis, University of Wales Swansea Computer Science Department, 1996.

    Google Scholar 

  32. K Stephenson. Algebraic specification of the Java virtual machine. In B Möller and J V Tucker, editors, Prospects for Hardware Foundations. Lecture Notes in Computer Science 1546, Springer-Verlag, 1998.

    Chapter  Google Scholar 

  33. P Windley and J Burch. Mechanically checking a lemma used in an automatic Verification tool. In A Camilleri M Srivas, editor, Formal Methods in Computer-Aided Design, pages 362–376. Lecture Notes in Computer Science 1166, Springer-Verlag, 1996.

    Chapter  Google Scholar 

  34. P Windley and M Coe. A correctness model for pipelined microprocessors. In Proceedings of the 2nd Conference on Theorem Provers in Circuit Design, 1994.

    Google Scholar 

  35. M Wirsing. Algebraic specification. In J van Leeuwen, editor, Handbook of Theoretical Computer Science, Volume B: Formal Models and Semantics, pages 675–788. Elsevier, 1990.

    Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science, University of Wales Swansea, Singleton Park, SA2 8PP, Swansea

    N. A. Harman

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  1. N. A. Harman
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  1. DISI -Dipartimento e Informatica di Scienze dell’Informazione, Università di Genova, Via Dodecaneso,35, 16146, Genova, Italy

    Maura Cerioli  & Gianna Reggio  & 

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Harman, N.A. (2002). Verifying a Simple Pipelined Microprocessor Using Maude. In: Cerioli, M., Reggio, G. (eds) Recent Trends in Algebraic Development Techniques. WADT 2001. Lecture Notes in Computer Science, vol 2267. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45645-7_7

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  • DOI: https://doi.org/10.1007/3-540-45645-7_7

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  • Print ISBN: 978-3-540-43159-6

  • Online ISBN: 978-3-540-45645-2

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