Abstract
This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
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Cantó, E., Moreno, J.M., Cabestany, J., Lacadena, I., Insenser, J.M. (2000). Implementation of Virtual Circuits by Means of the FIPSOC Devices. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_10
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DOI: https://doi.org/10.1007/3-540-44614-1_10
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