Abstract
The ODYSSEY design methodology has been recently introduced as a viable solution to the increasing design complexity problem in the ASICs. It is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these methods are implemented in hardware; others are simply executed by a general purpose processor. One fundamental element of this methodology is a network on chip that implements method invocation for hardware-based method calls. However this network is prone to faults, thus errors on it may result into system failure.
In this paper an architectural fault-tolerance enhancement to the ODYSSEY design methodology is proposed which covers this problem. It detects and corrects all single event upset errors on the network, and detects all permanent ones. The proposed enhancement is modeled analytically and then simulated. The simulation results, while validating the analytical model, show very low network performance overhead.
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References
International Technology Roadmap for Semiconductors (ITRS)-Design (2001), http:// public. itrs. net/Files/2002Update/2001ITRS/Design.pdf
Vellanki, P., et al.: Quality-of-service and error control techniques for mesh-based network-on-chip architectures. INTEGRATION, the VLSI journal 38, 353–382 (2005)
Dally, W., Poulton, J.: Digital Systems Engineering. Cambridge University Press, Cambridge (1998)
Taur, Y., et al.: CMOS scaling into the nanometer regime. In: Proc. of the IEEE, vol. 85 (April 1997)
Goudarzi, M., Hessabi, S., Mycroft, A.: Overhead-free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models. In: Proc. of Design Automation and Test in Europe (DATE 2004), Paris (February 2004)
Goudarzi, M., Hessabi, S.: Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs. Journal of Universal Computer Science (JUCS) (September 2004)
Dumitras, T., Kerner, S., Marculescu, R.: Towards onchip fault-tolerant communication. In: Proc. Asia and South Pacific Design Automation Conference (2003)
Hedetniemi, S.M., Hedetniemi, T., Liestman, A.L.: A survey of gossiping and broadcasting in communication networks. NETWORKS 18, 319–349 (1988)
Krumme, D.W., Cybenko, G., Venkataraman, K.N.: Gossiping in minimal time. SIAM J. Comput. 21(1), 111–139 (1992)
Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: DATE, Paris, France (March 2000)
Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabeay, J., Sangiovanni-Vincentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proceedings of Design Automation Conference, pp. 667–672 (June 2001)
Dally, W.J., Towles, B.: Route packet, not wires: on-chip interconnection networks. In: Proceedings of DAC (June 2002)
Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput., 70–78 (2002)
Kumar, S., Jantsch, A., Millberg, M., Oberg, J., Soininen, J.P., Forsell, M., Hemani, K.T.A.: A network on chip architecture and design methodology. In: IEEE Computer Society Annual Symposium, on VLSI, Pittsburg, Pennsylvania (April 2002)
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Fazeli, M., Farivar, R., Hessabi, S., Miremadi, S.G. (2005). A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems. In: Maziero, C.A., Gabriel Silva, J., Andrade, A.M.S., de Assis Silva, F.M. (eds) Dependable Computing. LADC 2005. Lecture Notes in Computer Science, vol 3747. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572329_13
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DOI: https://doi.org/10.1007/11572329_13
Publisher Name: Springer, Berlin, Heidelberg
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