Technical Paper Link, Author at Semiconductor Engineering

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3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

SW-HW Co-Design Mitigation To Strengthen ASLR Against Microarchitectural Attacks (MIT)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A technical paper titled "Oreo: Protecting ASLR Against Microarchitectural Attacks" was published by researchers at MIT. Abstract "Address Space Layout Randomization (ASLR) is one of the most prominently deployed mitigations against memory corruption attacks. ASLR randomly shuffles program virtual addresses to prevent attackers from knowing the location of program contents in memory. Microa... » read more

Low-Temp Pressure-Assisted Liquid-Metal Printing for Oxide-TFTs
By Technical Paper Link - 25 Feb, 2025 - Comments: 0

A new technical paper titled "Low-temperature pressure-assisted liquid-metal printing for β-Ga2O3 thin-film transistors" was published by researchers at UCSD and National Tsing Hua University. Abstract "Developing a low-temperature and cost-effective manufacturing process for energy-efficient and high-performance oxide-thin-film transistors (TFTs) is a crucial step toward advanci... » read more

Machine Learning-Based IR Drop Prediction Approach
By Technical Paper Link - 25 Feb, 2025 - Comments: 0

A new technical paper titled "Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate" was published by researchers at KTH Royal Institute of Technology and Ericsson Research. ABSTRACT "Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complex... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Cradle-To-Grave Analysis Of The Carbon Footprint of AI Hardware (Google)
By Technical Paper Link - 24 Feb, 2025 - Comments: 0

A new technical paper titled "Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends" was published by researchers at Google. Abstract "Specialized hardware accelerators aid the rapid advancement of artificial intelligence (AI), and their efficiency impacts AI's environmental sustainability. This study presents the first publication of a comprehensive AI acc... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

CFETs with Optimized Buried Power Rails
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

Low-Temperature Solid-Liquid Interdiffusion Bonding For High-Density Interconnect Applications
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Facilitating Small-Pitch Interconnects with Low-Temperature Solid-Liquid Interdiffusion Bonding" was published by researchers at Aalto University in Finland. Abstract "The trend for 3D heterogeneous integration drives the need for a low-temperature bonding process for high-density interconnects (HDI). The Cu-Sn-In based solid-liquid interdiffusion (SLID) is a p... » read more

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