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. 2021 Oct 20;12(11):1277.
doi: 10.3390/mi12111277.

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

Stefan Pechmann  1 , Timo Mai  2 , Julian Potschka  2 , Daniel Reiser  3 , Peter Reichel  4 , Marco Breiling  5 , Marc Reichenbach  6 , Amelie Hagelauer  7   8
Affiliations

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

Stefan Pechmann et al. Micromachines (Basel). .

Abstract

Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies.

Keywords: ANN; RRAM; embedded memory; low-power; memory block; multi-level.

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Conflict of interest statement

The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

Figures

Figure 1
Figure 1
Overview of a system utilizing ANN (blue) and the presented RRAM memory block (green) for AFib detection in sampled ECG signals. The RRAM memory blocks store the weight and bias values for the ANN in a non-volatile way to enable power gating for the processing core in general and the memory blocks individually after loading the values into the ANN [12].
Figure 2
Figure 2
Block diagram of the memory block. The digital inputs are marked in red, the outputs in green and the internal analog signals in blue. A logic block sets several control signals for the operational amplifier (opamp), the memory cells, and the reference block. The power supply control connects or disconnects the whole memory block from the supply rails according to the power enable signal pwr_en.
Figure 3
Figure 3
System waveforms: the operation<0:2> bits determine the voltage levels, while the cell_sel<0:31> signals activate the cells to interact with. The pulse_en signal triggers the operation, while pwr_en is used to switch the memory block on and off.
Figure 4
Figure 4
Components of the memory block: (a) memory cell, (b) set_reset switch.
Figure 5
Figure 5
Operational Amplifier: (a) block diagram of the amplifier (b) circuit of the 3.3 V output stage.
Figure 6
Figure 6
Implementation of the power control to reduce leakage current.
Figure 7
Figure 7
Simulation results of operational amplifier: (a): DC sweep of input voltage; (b): transient simulation of read sequence.
Figure 8
Figure 8
System simulation of a set and reset operation with read operations in between to evaluate the cell state.
See this image and copyright information in PMC

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