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. 2011 May 31:5:73.
doi: 10.3389/fnins.2011.00073. eCollection 2011.

Neuromorphic silicon neuron circuits

Giacomo Indiveri  1 , Bernabé Linares-Barranco, Tara Julia Hamilton, André van Schaik, Ralph Etienne-Cummings, Tobi Delbruck, Shih-Chii Liu, Piotr Dudek, Philipp Häfliger, Sylvie Renaud, Johannes Schemmel, Gert Cauwenberghs, John Arthur, Kai Hynna, Fopefolu Folowosele, Sylvain Saighi, Teresa Serrano-Gotarredona, Jayawan Wijekoon, Yingxue Wang, Kwabena Boahen
Affiliations

Neuromorphic silicon neuron circuits

Giacomo Indiveri et al. Front Neurosci. .

Abstract

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Keywords: adaptive exponential; analog VLSI; circuit; conductance based; integrate and fire; log-domain; spiking; subthreshold.

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Figures

Figure 1
Figure 1
(A) “Tau-cell” circuit: log-domain circuit used to implement a first-order low-pass filter (LPF); (B) Sub-threshold first-order LPF circuit; (C) “DPI” circuit: non-linear current-mode LPF circuit.
Figure 2
Figure 2
Thermodynamic model of a gating variable. (A) Gating variable circuit. (B) Voltage dependence of the steady-state and time-constant of the variable circuit in (A). See Hynna and Boahen (2007) for details.
Figure 3
Figure 3
Axon-hillock circuit. (A) Schematic diagram; (B) Membrane voltage and output voltage traces over time.
Figure 4
Figure 4
Voltage-amplifier I&F neuron. (A) Schematic diagram; (B) Membrane voltage trace over time.
Figure 5
Figure 5
Spike-frequency adaptation is a SiN. (A) Negative slow ionic current mechanism: The plot shows the instantaneous firing rate as a function of spike count. The inset shows how the individual spikes increase their inter-spike interval, with time. Figure adapted from Indiveri et al. (2010). (B) Adaptive threshold mechanism: The neuron's spiking threshold increases with every spike, therefore increasing the inter-spike interval with time.
Figure 6
Figure 6
Dendritic membrane circuit and cable circuit connecting the compartments. The “+” blocks indicate neighboring compartments. The block to which Iden flows into is similar to the circuit in Figure 2A.
Figure 7
Figure 7
(A) Digi-MOS: MOS transistor with digitally adjustable size factor (W/L)eff. Example five-bit implementation using MOS ladder techniques (B) Digi-MOS circuit symbol; (C) Very low current mirror: Circuit with negative gate-to-source voltage biasing for copying very low currents.
Figure 8
Figure 8
Two-compartment Thalamic relay neuron model. (A) Neuron circuit. (B,C) Dendritic voltage (Vmem) measurements of the relay cell's two response modes: burst (B) and tonic (C). An 80-ms wide current step is injected into the dendritic compartment at 10 ms in both cases.
Figure 9
Figure 9
(A) Translinear circuit implementing gated conductances of the form x3yg used to implement H–H conductance equations (Hodgkin and Huxley, 1952). (B) Steady-state (in)activation functions measured on the sub-threshold H–H neuron (figure adapted from Yu and Cauwenberghs, 2010a).
Figure 10
Figure 10
The octopus retina neuron. The input current is generated by a photodetector, while the spike generator uses positive current feedback to accelerate input and output transitions to minimize short-circuit currents during spike production. The membrane capacitance (Cmem) is disconnected from the input of the spike generator to further accelerate transition and to reduce power during reset.
Figure 11
Figure 11
Dynamic vision sensor (DVS) complementary ON–OFF differencing neuron. ON and OFF events are produced by quantized increases and decreases of log intensity since the last event from the pixel. The ON/OFF events are reset by row and column acknowledge signals VCA and VRA, which produces a reset pulse of a duration controlled by Vrefr. The mismatches in the comparator thresholds of ≈20 mV is reduced by a factor of the gain of 20 in the switched-capacitor differencing amplifier, resulting in an effective threshold mismatch of about 1 mV at Vp.
Figure 12
Figure 12
The tau-cell neuron circuit.
Figure 13
Figure 13
The log-domain LPF neuron (LLN). (A) The LLN circuit comprises a membrane LPF (yellow, ML1−3), a spike-event generation and positive-feedback element (red, MA1−6), a reset-refractory pulse generator (blue, MR1−3), and a spike-frequency adaptation LPF (green, MG1−4). (B) Recorded and normalized traces from a LLN fabricated in 0.25 μm CMOS, exhibits regular spiking, spike-frequency adaptation, and bursting (top to bottom).
Figure 14
Figure 14
The DPI neuron circuit. (A) Circuit schematic. The input DPI low-pass filter (yellow, ML1 − ML3) models the neuron's leak conductance. A spike event generation amplifier (red, MA1 − MA6) implements current-based positive feedback (modeling both sodium activation and inactivation conductances) and produces address-events at extremely low-power. The reset block (blue, MR1 − MR6) resets the neuron and keeps it in a reset state for a refractory period, set by the Vref bias voltage. An additional DPI filter integrates the spikes and produces a slow after hyper-polarizing current Ig responsible for spike-frequency adaptation (green, MG1 − MG6). (B) Response of the DPI neuron circuit to a constant input current. The measured data was fitted with a function comprising an exponential ∝e−t/τK at the onset of the stimulation, characteristic of all conductance-based models, and an additional exponential ∝e+t/τNa (characteristic of exponential I&F computational models; Brette and Gerstner, 2005) at the onset of the spike (Indiveri et al., 2010).
Figure 15
Figure 15
(A) Schematic of a “sigmoid” circuit. The Ish biasing current is set by the Vsh voltage input. From the multiplier Q1,Q2,Q11,Q12,QSig is proportional to (Vm − Voh)/Ish. From Q3−Q4 differential pair, Ih8 and I(1−h8)\ are complementary sigmoidal functions of Vsig, used for inactivation and activation variables, respectively. (B) A 600-ms simulation of a four-conductance silicon neuron with an input stimulation current pulse: (a) Membrane voltage Vm(t). (b) Calcium current ICa(t). (c) Stimulation current IS(t). Sodium and potassium and leak conductances generate the action potentials; a calcium conductance with a slow kinetic modulates the action potential occurrence. Individual ionic currents are available for monitoring. Voltage and current scales are the biological model scales. Hardware and biological time scales are identical, as the simulation runs in continuous and real time. When the stimulation current is applied, the neuron starts oscillating and the calcium current increases, which in turn raises the oscillation frequency. At the end of the stimulation pulse, oscillations continue until the calcium current is low enough. Finally, the neuronal activity ceases.
Figure 16
Figure 16
The Izhikevich neuron circuit (A) schematic diagram, (B) data recorded from the 0. 35 μm CMOS VLSI implementation: spiking patterns in response to input current step for various parameters of bias voltages at node c and node d: regular spiking with adaptation, fast spiking, intrinsically bursting, chattering (top to bottom).
Figure 17
Figure 17
Accelerated current-controlled conductance neuron. (A) Schematic diagram: excitatory and inhibitory synaptic inputs can be connected as an array of current-sinks to the Iinhib or Iexc nodes. The passive leak behavior is controlled via the Ileak node. (B) Measured response of the membrane potential to 256 Poisson distributed input spike trains, compared to an equivalent software simulation. The chip is calibrated to an acceleration factor of 104. Top: input spike trains with 8 Hz mean firing rate in biological time. Middle: membrane voltage calculated with the software simulator NEST (Eppler et al., 2008). Bottom: membrane voltage recorded from the hardware neuron.
Figure 18
Figure 18
Switched-capacitor Mihalas–Niebur neuron implementation. (A) Neuron membrane circuits; (B) adaptive threshold circuits.
Figure 19
Figure 19
S-C Mihalas–Niebur neuron circuit results demonstrating 10 of the known spiking properties that have been observed in biological neurons. Membrane voltage and adaptive threshold are illustrated in blue and black respectively. (A) – tonic spiking, (B) – class 1 spiking, (C) – spike-frequency adaptation, (D) – phasic spiking, (E) – accommodation, (F) – threshold variability, (G) – rebound spiking, (H) – input bistability, (I) – integrator, (J) – hyper-polarized spiking.
Figure 20
Figure 20
(A) Digitally weight-modulated and calibrated charge packet driven leaky I&F neuron schematic. The neuron handles positive and negative charge packets to emulate excitatory and inhibitory synapses, and has input for a periodic global signal PulseF to implement a programmable constant rate leak. Neuron can deliver positive or negative output events. (B) Detail of logic block in (A).
Figure 21
Figure 21
Block diagram of a fully digital I&F neuron. Calibrated current source, pulsing current mirrors, and integration capacitors of Figure 20, are replaced by digital adder and accumulator circuits.
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References

    1. Arthur J. V., Boahen K. (2004). Recurrently connected silicon neurons with active dendrites for one-shot learning. IEEE Int. Joint Conf. Neural Netw. 3, 1699–1704
    1. Arthur J. V., Boahen K. (2007). Synchrony in silicon: the gamma rhythm. IEEE Trans. Neural Netw. 18, 1815–182510.1109/TNN.2007.900238 - DOI - PubMed
    1. Azadmehr M., Abrahamsen J. P., Hafliger P. (2005). “A foveated AER imager chip,” in International Symposium on Circuits and Systems, ISCAS 2005, Vol. 3 (Kobe: IEEE; ), 2751–2754 - PubMed
    1. Bartolozzi C., Indiveri G. (2007). Synaptic dynamics in analog VLSI. Neural Comput. 19, 2581–260310.1162/neco.2007.19.10.2581 - DOI - PubMed
    1. Bartolozzi C., Indiveri G. (2009). Global scaling of synaptic efficacy: homeostasis in silicon synapses. Neurocomputing 72, 726–73110.1016/j.neucom.2008.05.016 - DOI