-----------------------------------------------------------------------------
--
-- AXI Slave
--
-----------------------------------------------------------------------------
-- 2012/02/25 : S_AXI_AWBURST＝1 (INCR) にのみ対応、AWSIZE, ARSIZE = 000 (1byte), 001 (2bytes), 010 (4bytes) のみ対応。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--library unisim;
--use unisim.vcomponents.all;
entity cdc_axi_slave is
generic (
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_AWUSER_WIDTH : integer := 1;
C_S_AXI_ARUSER_WIDTH : integer := 1;
C_S_AXI_WUSER_WIDTH : integer := 1;
C_S_AXI_RUSER_WIDTH : integer := 1;
C_S_AXI_BUSER_WIDTH : integer := 1
);
port(
-- System Signals
ACLK : in std_logic;
ARESETN : in std_logic;
-- Slave Interface Write Address Ports
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(8-1 downto 0);
S_AXI_AWSIZE : in std_logic_vector(3-1 downto 0);
S_AXI_AWBURST : in std_logic_vector(2-1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(2-1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(4-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(3-1 downto 0);
S_AXI_AWREGION : in std_logic_vector(4-1 downto 0);
S_AXI_AWQOS : in std_logic_vector(4-1 downto 0);
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- Slave Interface Write Data Ports
S_AXI_WID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- Slave Interface Write Response Ports
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(2-1 downto 0);
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- Slave Interface Read Address Ports
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(8-1 downto 0);
S_AXI_ARSIZE : in std_logic_vector(3-1 downto 0);
S_AXI_ARBURST : in std_logic_vector(2-1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(2-1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(4-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(3-1 downto 0);
S_AXI_ARREGION : in std_logic_vector(4-1 downto 0);
S_AXI_ARQOS : in std_logic_vector(4-1 downto 0);
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- Slave Interface Read Data Ports
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(2-1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- TMDS Signals
pixclk : in std_logic;
TMDS_tx_clk_p : out std_logic; -- Clock
TMDS_tx_clk_n : out std_logic;
TMDS_tx_2_G_p : out std_logic; -- Green
TMDS_tx_2_G_n : out std_logic;
TMDS_tx_1_R_p : out std_logic; -- Red
TMDS_tx_1_R_n : out std_logic;
TMDS_tx_0_B_p : out std_logic; -- Blue
TMDS_tx_0_B_n : out std_logic
);
end cdc_axi_slave;
architecture implementation of cdc_axi_slave is
component dvi_disp
generic (
PLL_CLKFBOUT_MULT : integer := 20; -- VGA解像度 PLL VCO Freq 400MHz ~ 1000MHz
PLL_CLKIN_PERIOD : real := 40.0; -- VGA ピクセルクロック周期
PLL_CLKOUT0_DIVIDE : integer := 2; -- ピクセルクロックX10
PLL_CLKOUT1_DIVIDE : integer := 20; -- ピクセルクロック
PLL_CLKOUT2_DIVIDE : integer := 10 -- ピクセルクロックX2
);
port (
pixclk : in std_logic; -- pixel clock
reset_in : in std_logic; -- active high
red_in : in std_logic_vector(7 downto 0); -- RED入力
green_in : in std_logic_vector(7 downto 0); -- GREEN入力
blue_in : in std_logic_vector(7 downto 0); -- BLUE入力
hsync : in std_logic;
vsync : in std_logic;
display_enable : in std_logic; -- 表示が有効
TMDS_tx_clk_p : out std_logic; -- Clock
TMDS_tx_clk_n : out std_logic;
TMDS_tx_2_G_p : out std_logic; -- Green
TMDS_tx_2_G_n : out std_logic;
TMDS_tx_1_R_p : out std_logic; -- Red
TMDS_tx_1_R_n : out std_logic;
TMDS_tx_0_B_p : out std_logic; -- Blue
TMDS_tx_0_B_n : out std_logic
);
end component;
component CharDispCtrler
port(
axi4clk : in std_logic;
pixclk : in std_logic;
reset : in std_logic;
processor_addr : in std_logic_vector(12 downto 0);
processor_din : in std_logic_vector(15 downto 0);
processor_dout : out std_logic_vector(15 downto 0);
processor_we : in std_logic;
VGA_RED : out std_logic_vector(2 downto 0);
VGA_GREEN : out std_logic_vector(2 downto 0);
VGA_BLUE : out std_logic_vector(2 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic;
display_enable : out std_logic
);
end component;
COMPONENT afifo_sm
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC
);
END COMPONENT;
constant AxBURST_FIXED : std_logic_vector := "00";
constant AxBURST_INCR : std_logic_vector := "01";
constant AxBURST_WRAP : std_logic_vector := "10";
constant RESP_OKAY : std_logic_vector := "00";
constant RESP_EXOKAY : std_logic_vector := "01";
constant RESP_SLVERR : std_logic_vector := "10";
constant RESP_DECERR : std_logic_vector := "11";
-- for write transaction
type write_transaction_state is (idle_wr, awr_wait, awr_accept, wr_burst);
type write_response_state is (idle_wres, bvalid_assert);
type write_wready_state is (idle_wrdy, wready_assert);
signal wrt_cs : write_transaction_state;
signal wrres : write_response_state;
signal wrwr : write_wready_state;
-- for read transaction
type read_transaction_state is (idle_rd, arr_wait, arr_accept, rd_burst);
type read_last_state is (idle_rlast, rlast_assert);
signal rdt_cs : read_transaction_state;
signal rdlast : read_last_state;
signal reset_1d, reset_2d, reset : std_logic := '1';
signal awready : std_logic;
signal wr_addr : std_logic_vector(12 downto 0);
signal wr_bid : std_logic_vector(0 downto 0);
signal wr_bresp : std_logic_vector(1 downto 0);
signal wr_bvalid : std_logic;
signal arready : std_logic;
signal rd_addr : std_logic_vector(12 downto 0);
signal rd_axi_count : std_logic_vector(7 downto 0);
signal rd_cdc_count : std_logic_vector(8 downto 0);
signal rdfifo_din : std_logic_vector(15 downto 0);
signal rdfifo_wr_en : std_logic;
signal rdfifo_rd_en : std_logic;
signal rdfifo_full, rdfifo_empty : std_logic;
signal rdfifo_almost_full, rdfifo_almost_empty : std_logic;
signal rdfifo_overflow, rdfifo_underflow : std_logic;
signal rvalid : std_logic;
signal rlast : std_logic;
signal cdc_addr : std_logic_vector(12 downto 0);
signal vga_red, vga_green, vga_blue : std_logic_vector(2 downto 0);
signal vga_red8, vga_green8, vga_blue8 : std_logic_vector(7 downto 0);
signal vga_hsync, vga_vsync : std_logic;
signal display_enable : std_logic;
signal cdc_we : std_logic;
signal rdfifo_wr_en_node : std_logic;
begin
-- ARESETN をACLK で同期化
process (ACLK) begin
if ACLK'event and ACLK='1' then
reset_1d <= not ARESETN;
reset_2d <= reset_1d;
end if;
end process;
reset <= reset_2d;
-- AXI4バス Write Transaction State Machine
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wrt_cs <= idle_wr;
awready <= '0';
else
case (wrt_cs) is
when idle_wr =>
if S_AXI_AWVALID='1' then -- S_AXI_AWVALID が1にアサートされた
if rdt_cs=idle_rd then -- Read Transaction が終了している（Writeの方が優先順位が高い）
wrt_cs <= awr_accept;
awready <= '1';
else -- Read Transaction が終了していないのでWait
wrt_cs <= awr_wait;
end if;
end if;
when awr_wait => -- Read Transaction の終了待ち
if rdt_cs=idle_rd or rdt_cs=arr_wait then -- Read Transaction が終了
wrt_cs <= awr_accept;
awready <= '1';
end if;
when awr_accept => -- S_AXI_AWREADY をアサート
wrt_cs <= wr_burst;
awready <= '0';
when wr_burst => -- Writeデータの転送
if S_AXI_WLAST='1' and S_AXI_WVALID='1' then -- Write Transaction 終了
wrt_cs <= idle_wr;
end if;
end case;
end if;
end if;
end process;
S_AXI_AWREADY <= awready;
S_AXI_WREADY <= '1' when wrt_cs=wr_burst else '0';
cdc_we <= '1' when wrt_cs=wr_burst and S_AXI_WVALID='1' else '0';
-- wr_addr の処理
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_addr <= (others => '0');
else
if wrt_cs=awr_accept then
wr_addr <= S_AXI_AWADDR(14 downto 2); -- 32ビット幅データのため
elsif wrt_cs=wr_burst and S_AXI_WVALID='1' then -- アドレスを１つ進める
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process;
-- wr_bid の処理
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_bid <= "0";
else
if wrt_cs=awr_accept then
wr_bid <= S_AXI_AWID;
end if;
end if;
end if;
end process;
S_AXI_BID <= wr_bid;
-- wr_bresp の処理
-- S_AXI_AWBURSTがINCRの時はOKAYを返す。それ以外はSLVERRを返す。
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_bresp <= (others => '0');
else
if wrt_cs=awr_accept then
if S_AXI_AWBURST=AxBURST_INCR then -- バーストタイプがアドレス・インクリメントタイプ
wr_bresp <= RESP_OKAY; -- Write Transaction は成功
else
wr_bresp <= RESP_SLVERR; -- エラー
end if;
end if;
end if;
end if;
end process;
S_AXI_BRESP <= wr_bresp;
-- wr_bvalid の処理
-- Write Transaction State Machineには含まない。axi_master のシミュレーションを見ると１クロックで終了しているので、長い間、Master側の都合でWaitしていることは考えない。
-- 次のWrite転送まで遅延しているようであれば、Write Transaction State Machine に入れてブロックすることも考える必要がある。
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_bvalid <= '0';
else
if S_AXI_WLAST='1' and S_AXI_WVALID='1' then -- Write Transaction 終了
wr_bvalid <= '1';
elsif wr_bvalid='1' and S_AXI_BREADY='1' then -- wr_bvalid が１でMaster側のReadyも１ならばWrite resonse channel の転送も終了
wr_bvalid <= '0';
end if;
end if;
end if;
end process;
S_AXI_BVALID <= wr_bvalid;
S_AXI_BUSER <= (others => '0');
-- AXI4バス Read Transaction State Machine
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rdt_cs <= idle_rd;
arready <= '0';
else
case (rdt_cs) is
when idle_rd =>
if S_AXI_ARVALID='1' then -- Read Transaction 要求
if wrt_cs=idle_wr and S_AXI_AWVALID='0' then -- Write Transaction State Machine がidle でWrite要求もない
rdt_cs <= arr_accept;
arready <= '1';
else -- Write Transaction が終了していないのでWait
rdt_cs <= arr_wait;
end if;
end if;
when arr_wait => -- Write Transaction の終了待ち
if wrt_cs=idle_wr and S_AXI_AWVALID='0' then -- Write Transaction State Machine がidle でWrite要求もない
rdt_cs <= arr_accept;
arready <= '1';
end if;
when arr_accept => -- S_AXI_ARREADY をアサート
rdt_cs <= rd_burst;
arready <= '0';
when rd_burst => -- Readデータの転送
if rd_axi_count=0 and rvalid='1' and S_AXI_RREADY='1' then -- Read Transaction 終了
rdt_cs <= idle_rd;
end if;
end case;
end if;
end if;
end process;
S_AXI_ARREADY <= arready;
-- rd_addr の処理
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rd_addr <= (others => '0');
else
if rdt_cs=arr_accept then
rd_addr <= S_AXI_ARADDR(14 downto 2); -- 32ビット幅データのため
elsif rdt_cs=rd_burst and rdfifo_almost_full='0' and rd_cdc_count/=0 then -- rdfifoに余裕があるときにはアドレスを1つ進める
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process;
-- Read用FIFOのインスタンス
rdfifo : afifo_sm PORT MAP (
clk => ACLK,
rst => reset,
din => rdfifo_din,
wr_en => rdfifo_wr_en,
rd_en => rdfifo_rd_en,
dout => S_AXI_RDATA(15 downto 0),
full => rdfifo_full,
almost_full => rdfifo_almost_full,
overflow => rdfifo_overflow,
empty => rdfifo_empty,
almost_empty => rdfifo_almost_empty,
underflow => rdfifo_underflow
);
S_AXI_RDATA(31 downto 16) <= (others => '0');
rvalid <= not rdfifo_empty;
S_AXI_RVALID <= rvalid;
rdfifo_wr_en_node <= '1' when rdt_cs=rd_burst and rdfifo_almost_full='0' and rd_cdc_count/=0 else '0';
-- BlockRAMのReadは1クロック遅延するため、1クロック遅延させる。
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rdfifo_wr_en <= '0';
else
rdfifo_wr_en <= rdfifo_wr_en_node;
end if;
end if;
end process;
rdfifo_rd_en <= '1' when rdt_cs=rd_burst and rvalid='1' and S_AXI_RREADY='1' else '0';
-- rd_cdc_count の処理（CDC側のデータカウント）
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rd_cdc_count <= (others => '0');
else
if rdt_cs=arr_accept then -- ロード
rd_cdc_count <= ('0'& S_AXI_ARLEN) + 1;
elsif rdt_cs=rd_burst and rdfifo_almost_full='0' and rd_cdc_count/=0 then -- FIFOに余裕がある
rd_cdc_count <= rd_cdc_count - 1;
end if;
end if;
end if;
end process;
-- rd_axi_count の処理（AXIバス側のデータカウント）
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rd_axi_count <= (others => '0');
else
if rdt_cs=arr_accept then -- rd_axi_count のロード
rd_axi_count <= S_AXI_ARLEN;
elsif rdt_cs=rd_burst and rvalid='1' and S_AXI_RREADY='1' then -- Read Transaction が1つ終了
rd_axi_count <= rd_axi_count - 1;
end if;
end if;
end if;
end process;
-- rdlast State Machine
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
rdlast <= idle_rlast;
rlast <= '0';
else
case (rdlast) is
when idle_rlast =>
if rd_axi_count=1 and rvalid='1' and S_AXI_RREADY='1' then -- バーストする場合
rdlast <= rlast_assert;
rlast <= '1';
elsif rdt_cs=arr_accept and S_AXI_ARLEN=0 then -- 転送数が1の場合
rdlast <= rlast_assert;
rlast <= '1';
end if;
when rlast_assert =>
if rvalid='1' and S_AXI_RREADY='1' then -- Read Transaction 終了（rd_axi_count=0は決定）
rdlast <= idle_rlast;
rlast <= '0';
end if;
end case;
end if;
end if;
end process;
S_AXI_RLAST <= rlast;
-- S_AXI_RID, S_AXI_RUSER の処理
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
S_AXI_RID <= (others => '0');
else
if rdt_cs=arr_accept then
S_AXI_RID <= S_AXI_ARID;
end if;
end if;
end if;
end process;
S_AXI_RUSER <= (others => '0');
-- S_AXI_RRESP は、S_AXI_ARBURST がINCR の場合はOKAYを返す。それ以外はSLVERRを返す。
process (ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
S_AXI_RRESP <= (others => '0');
else
if rdt_cs=arr_accept then
if S_AXI_ARBURST=AxBURST_INCR then
S_AXI_RRESP <= RESP_OKAY;
else
S_AXI_RRESP <= RESP_SLVERR;
end if;
end if;
end if;
end if;
end process;
-- CharDispCtrler
cdc_addr <= wr_addr when rdt_cs=idle_rd or rdt_cs=arr_wait else rd_addr;
CDC_inst : CharDispCtrler port map (
axi4clk => ACLK,
pixclk => pixclk,
reset => reset,
processor_addr => cdc_addr,
processor_din => S_AXI_WDATA(15 downto 0),
processor_dout => rdfifo_din,
processor_we => cdc_we,
VGA_RED => vga_red,
VGA_GREEN => vga_green,
VGA_BLUE => vga_blue,
VGA_HSYNC => vga_hsync,
VGA_VSYNC => vga_vsync,
display_enable => display_enable
);
-- dvi_disp
-- VGA解像度 PLL VCO Freq=400MHz ~ 1000MHz なので、25MHz入力クロックだと最初に20倍する必要がある。
-- XGA 解像度だと、PLL_CLKFBOUT_MULT=20だと、PLL VCO Freq=1300MHzとなり、1000MHzを超えるので、10倍に変更する。
dvi_disp_inst : dvi_disp generic map (
-- PLL_CLKFBOUT_MULT => 20, -- VGA
-- PLL_CLKIN_PERIOD => 40.0,
-- PLL_CLKOUT0_DIVIDE => 2,
-- PLL_CLKOUT1_DIVIDE => 20,
-- PLL_CLKOUT2_DIVIDE => 10
PLL_CLKFBOUT_MULT => 20, -- SVGA
PLL_CLKIN_PERIOD => 25.0,
PLL_CLKOUT0_DIVIDE => 2,
PLL_CLKOUT1_DIVIDE => 20,
PLL_CLKOUT2_DIVIDE => 10
-- PLL_CLKFBOUT_MULT => 10, -- XGA
-- PLL_CLKIN_PERIOD => 15.4,
-- PLL_CLKOUT0_DIVIDE => 1,
-- PLL_CLKOUT1_DIVIDE => 10,
-- PLL_CLKOUT2_DIVIDE => 5
-- PLL_CLKFBOUT_MULT => 10, -- SXGA(-3スピードグレードのみ）
-- PLL_CLKIN_PERIOD => 9.3,
-- PLL_CLKOUT0_DIVIDE => 1,
-- PLL_CLKOUT1_DIVIDE => 10,
-- PLL_CLKOUT2_DIVIDE => 5
) port map (
pixclk => pixclk,
reset_in => reset,
red_in => vga_red8,
green_in => vga_green8,
blue_in => vga_blue8,
hsync => vga_hsync,
vsync => vga_vsync,
display_enable => display_enable,
TMDS_tx_clk_p => TMDS_tx_clk_p,
TMDS_tx_clk_n => TMDS_tx_clk_n,
TMDS_tx_2_G_p => TMDS_tx_2_G_p,
TMDS_tx_2_G_n => TMDS_tx_2_G_n,
TMDS_tx_1_R_p => TMDS_tx_1_R_p,
TMDS_tx_1_R_n => TMDS_tx_1_R_n,
TMDS_tx_0_B_p => TMDS_tx_0_B_p,
TMDS_tx_0_B_n => TMDS_tx_0_B_n
);
vga_red8 <= vga_red & "00000";
vga_green8 <= vga_green & "00000";
vga_blue8 <= vga_blue & "00000";
end implementation;
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Sat Feb 25 06:45:30 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:8.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=true
CSET almost_full_flag=true
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=afifo_sm
CSET data_count=false
CSET data_count_width=5
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_handshake_flag_options_axis=false
CSET enable_handshake_flag_options_rach=false
CSET enable_handshake_flag_options_rdch=false
CSET enable_handshake_flag_options_wach=false
CSET enable_handshake_flag_options_wdch=false
CSET enable_handshake_flag_options_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Distributed_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=15
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=14
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=16
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=16
CSET output_depth=16
CSET overflow_flag=true
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
CSET programmable_full_type_wach=Full
CSET programmable_full_type_wdch=Full
CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=5
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=true
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=5
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-10-22T06:08:52Z
# END Extra information
GENERATE
# CRC: 76cfed70
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