galileo7のWattmeter２の平均値と実効値を評価した。平均値はシリコンブリッジのロス？があり、低い電流では特に誤差が大きい。ただし、10Aの出力電圧を見るとリニアであれば50Aくらいまで測れそう。 http://ow.ly/9kANV
実効値は低い電流から10Aぐらいまで誤差が本当に少なく（クランプメーターと比べて）測ることができるみたいだ。ただし、出力は交流をサンプリングしているせいもあり、付いている抵抗だと15Aがmaxっぽい。
抵抗を110Ωに下げて、（元は330Ω）スケッチをそれなりに変更すると、やはり50Aくらいまで測れそうな波形になる。低い電流も結構行けそうだ。クランプセンサのデータシートを調べて、これで行ければ、これで行こうと思う。
Arduinoのシールドのお話でした。
Digilentのdigilentライブラリが面倒なので、workライブラリに修正してしまった。
さて、AXIバス・スレーブはインターコネクトを通して、マスタにつながるが、テストベンチとして仮マスタをtaskで作って、スレーブ回路をテストする。
完全にtaskで作ると、トランザクションをオーバラップできない（実は書けるのだろうか？）ので、always文と組み合わせて構築中。
OPTION DESC = CDC_AXI Slave
OPTION LONG_DESC = CDC_AXI Slave
// SVGA 解像度
parameter H_ACTIVE_VIDEO= 800;
parameter H_FRONT_PORCH = 40;
parameter H_SYNC_PULSE = 128;
parameter H_BACK_PORCH = 88;
parameter H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter V_ACTIVE_VIDEO = 600;
parameter V_FRONT_PORCH = 1;
parameter V_SYNC_PULSE = 4;
parameter V_BACK_PORCH = 23;
parameter V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
process(clk) begin -- キャラクタコードを＋1して表示
if clk'event and clk='1' then
if reset='1' then
processor_addr <= (others => '0');
else
if ena='1' then
-- if processor_addr=CONV_STD_LOGIC_VECTOR(4799, 13) then -- 終了(VGA)
if processor_addr=CONV_STD_LOGIC_VECTOR(7499, 13) then -- 終了(SVGA)
processor_addr <= (others => '0');
else
processor_addr <= processor_addr + 1;
end if;
end if;
end if;
end if;
end process;
parameter H_ACTIVE_VIDEO= 1024;
parameter H_FRONT_PORCH = 24;
parameter H_SYNC_PULSE = 136;
parameter H_BACK_PORCH = 160;
parameter H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter V_ACTIVE_VIDEO = 768;
parameter V_FRONT_PORCH = 2;
parameter V_SYNC_PULSE = 6;
parameter V_BACK_PORCH = 29;
parameter V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
process(clk) begin -- キャラクタコードを＋1して表示
if clk'event and clk='1' then
if reset='1' then
processor_addr <= (others => '0');
else
if ena='1' then
-- if processor_addr=CONV_STD_LOGIC_VECTOR(4799, 13) then -- 終了(VGA)
-- if processor_addr=CONV_STD_LOGIC_VECTOR(7499, 13) then -- 終了(SVGA)
if processor_addr=CONV_STD_LOGIC_VECTOR(8191, 13) then -- 足りないが終了(XGA)
processor_addr <= (others => '0');
else
processor_addr <= processor_addr + 1;
end if;
end if;
end if;
end if;
end process;
dvi_disp_inst : dvi_disp generic map (
PLL_CLKFBOUT_MULT => 10, -- XGA
PLL_CLKIN_PERIOD => 15.4,
PLL_CLKOUT0_DIVIDE => 1,
PLL_CLKOUT1_DIVIDE => 10,
PLL_CLKOUT2_DIVIDE => 5
) port map (
// SXGA 解像度
parameter H_ACTIVE_VIDEO= 1280;
parameter H_FRONT_PORCH = 48;
parameter H_SYNC_PULSE = 112;
parameter H_BACK_PORCH = 248;
parameter H_SUM = H_ACTIVE_VIDEO + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter V_ACTIVE_VIDEO = 1024;
parameter V_FRONT_PORCH = 1;
parameter V_SYNC_PULSE = 3;
parameter V_BACK_PORCH = 38;
parameter V_SUM = V_ACTIVE_VIDEO + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
-- dvi_disp.vhd
-- Verilog版とは違ってDigilent 社のDVITransmitter.vhd を使用する
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dvi_disp is
generic (
PLL_CLKFBOUT_MULT : integer := 20; -- VGA解像度 PLL VCO Freq 400MHz ~ 1000MHz
PLL_CLKIN_PERIOD : real := 40.0; -- VGA ピクセルクロック周期
PLL_CLKOUT0_DIVIDE : integer := 2; -- ピクセルクロックX10
PLL_CLKOUT1_DIVIDE : integer := 20; -- ピクセルクロック
PLL_CLKOUT2_DIVIDE : integer := 10 -- ピクセルクロックX2
);
port (
pixclk : in std_logic; -- pixel clock
reset_in : in std_logic; -- active high
red_in : in std_logic_vector(7 downto 0); -- RED入力
green_in : in std_logic_vector(7 downto 0); -- GREEN入力
blue_in : in std_logic_vector(7 downto 0); -- BLUE入力
hsync : in std_logic;
vsync : in std_logic;
display_enable : in std_logic; -- 表示が有効
TMDS_tx_clk_p : out std_logic; -- Clock
TMDS_tx_clk_n : out std_logic;
TMDS_tx_2_G_p : out std_logic; -- Green
TMDS_tx_2_G_n : out std_logic;
TMDS_tx_1_R_p : out std_logic; -- Red
TMDS_tx_1_R_n : out std_logic;
TMDS_tx_0_B_p : out std_logic; -- Blue
TMDS_tx_0_B_n : out std_logic
);
end dvi_disp;
architecture RTL of dvi_disp is
component PLL_BASE
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 1;
CLKFBOUT_PHASE : real := 0.0;
CLKIN_PERIOD : real := 0.000;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
LOCKED : out std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic
);
end component;
component BUFPLL
generic (
DIVIDE : integer := 1;
ENABLE_SYNC : boolean := TRUE
);
port (
IOCLK : out std_ulogic;
LOCK : out std_ulogic;
SERDESSTROBE : out std_ulogic;
GCLK : in std_ulogic;
LOCKED : in std_ulogic;
PLLIN : in std_ulogic
);
end component;
component DVITransmitter
port (
RED_I : in STD_LOGIC_VECTOR (7 downto 0);
GREEN_I : in STD_LOGIC_VECTOR (7 downto 0);
BLUE_I : in STD_LOGIC_VECTOR (7 downto 0);
HS_I : in STD_LOGIC;
VS_I : in STD_LOGIC;
VDE_I : in STD_LOGIC;
PCLK_I : in STD_LOGIC;
PCLK_X2_I : in STD_LOGIC;
SERCLK_I : in STD_LOGIC;
SERSTB_I : in STD_LOGIC;
TMDS_TX_CLK_P : out STD_LOGIC;
TMDS_TX_CLK_N : out STD_LOGIC;
TMDS_TX_2_P : out STD_LOGIC;
TMDS_TX_2_N : out STD_LOGIC;
TMDS_TX_1_P : out STD_LOGIC;
TMDS_TX_1_N : out STD_LOGIC;
TMDS_TX_0_P : out STD_LOGIC;
TMDS_TX_0_N : out STD_LOGIC
);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic
);
end component;
signal pll_clkfg : std_logic;
signal pixel_clk, pixel_clkx10, pixel_clkx2 : std_logic;
signal pll_locked : std_logic;
signal pclk_bufg, pclkx2_bufg : std_logic;
signal bufpll_locked : std_logic;
signal serdes_strobe : std_logic;
signal pixel_clkio : std_logic;
begin
PLL_BASE_PIXEL : PLL_BASE generic map (
CLKFBOUT_MULT => PLL_CLKFBOUT_MULT,
COMPENSATION => "INTERNAL",
CLKIN_PERIOD => PLL_CLKIN_PERIOD,
CLKOUT0_DIVIDE => PLL_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => PLL_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => PLL_CLKOUT2_DIVIDE
) port map (
CLKFBOUT => pll_clkfg,
CLKOUT0 => pixel_clkx10,
CLKOUT1 => pixel_clk,
CLKOUT2 => pixel_clkx2,
LOCKED => pll_locked,
CLKFBIN => pll_clkfg,
CLKIN => pixclk,
RST => reset_in
);
BUFG_pixel_clk : BUFG port map (
O => pclk_bufg,
I => pixel_clk
);
BUFG_pixel_clkx2 : BUFG port map (
O => pclkx2_bufg,
I => pixel_clkx2
);
BUFPLL_pixel : BUFPLL generic map (
DIVIDE => 5,
ENABLE_SYNC => TRUE
) port map (
IOCLK => pixel_clkio,
LOCK => bufpll_locked,
SERDESSTROBE => serdes_strobe,
GCLK => pclkx2_bufg,
LOCKED => pll_locked,
PLLIN => pixel_clkx10
);
DVI_TX : DVITransmitter port map (
RED_I => red_in,
GREEN_I => green_in,
BLUE_I => blue_in,
HS_I => hsync,
VS_I => vsync,
VDE_I => display_enable,
PCLK_I => pclk_bufg,
PCLK_X2_I => pclkx2_bufg,
SERCLK_I => pixel_clkio,
SERSTB_I => serdes_strobe,
TMDS_TX_CLK_P => TMDS_tx_clk_p,
TMDS_TX_CLK_N => TMDS_tx_clk_n,
TMDS_TX_2_P => TMDS_tx_2_G_p,
TMDS_TX_2_N => TMDS_tx_2_G_n,
TMDS_TX_1_P => TMDS_tx_1_R_p,
TMDS_TX_1_N => TMDS_tx_1_R_n,
TMDS_TX_0_P => TMDS_tx_0_B_p,
TMDS_TX_0_N => TMDS_tx_0_B_n
);
end RTL;
-- CharDispCtrlerTest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity CharDispCtrlerTest is
generic(
ENABLE_COUNT : integer := 250000
);
port (
clk : in std_logic;
reset : in std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic;
display_enable : out std_logic
);
end CharDispCtrlerTest;
architecture RTL of CharDispCtrlerTest is
component CharDispCtrler
port(
clk : in std_logic;
reset : in std_logic;
processor_addr : in std_logic_vector(12 downto 0);
processor_din : in std_logic_vector(9 downto 0);
processor_dout : out std_logic_vector(9 downto 0);
processor_we : in std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic;
display_enable : out std_logic
);
end component;
signal processor_addr : std_logic_vector(12 downto 0);
signal processor_din : std_logic_vector(9 downto 0);
signal processor_dout : std_logic_vector(9 downto 0);
signal processor_we : std_logic;
signal count : std_logic_vector(22 downto 0);
signal ena : std_logic;
signal char_code : std_logic_vector(6 downto 0);
signal color_data : std_logic_vector(2 downto 0);
begin
CharDispCtrler_inst : CharDispCtrler port map(
clk => clk,
reset => reset,
processor_addr => processor_addr,
processor_din => processor_din,
processor_dout => processor_dout,
processor_we => processor_we,
VGA_RED => VGA_RED,
VGA_GREEN => VGA_GREEN,
VGA_BLUE => VGA_BLUE,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC,
display_enable => display_enable
);
process(clk) begin
if clk'event and clk='1' then
if reset='1' then
count <= (others => '0');
ena <= '0';
else
if count = ENABLE_COUNT then
count <= (others => '0');
ena <= '1';
else
count <= count + 1;
ena <= '0';
end if;
end if;
end if;
end process;
process(clk) begin -- キャラクタコードを＋1して表示
if clk'event and clk='1' then
if reset='1' then
processor_addr <= (others => '0');
else
if ena='1' then
if processor_addr=CONV_STD_LOGIC_VECTOR(4799, 13) then -- 終了
processor_addr <= (others => '0');
else
processor_addr <= processor_addr + 1;
end if;
end if;
end if;
end if;
end process;
process(clk) begin -- キャラクタコードを＋1して表示
if clk'event and clk='1' then
if reset='1' then
char_code <= "0100001"; -- キャラクタの!
else
if ena='1' then
if char_code="1111110" then -- キャラクタの~
char_code <= "0100001"; -- キャラクタの!
else
char_code <= char_code + 1;
end if;
end if;
end if;
end if;
end process;
process(clk) begin -- 色を+1しながら表示
if clk'event and clk='1' then
if reset='1' then
color_data <= "001";
else
if ena='1' then
if color_data="111" then
color_data <= "001"; -- 0 は非表示
else
color_data <= color_data + 1;
end if;
end if;
end if;
end if;
end process;
processor_din <= color_data & char_code;
processor_we <= ena;
end RTL;
-- CharDispCtrlerTest_HDMI.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library digilent;
use digilent.Video.ALL;
entity CharDispCtrlerTest_HDMI is
generic(
ENABLE_COUNT : integer := 250000
);
port(
sysclk : in std_logic;
reset_sw : in std_logic;
TMDS_tx_clk_p : out std_logic; -- Clock
TMDS_tx_clk_n : out std_logic;
TMDS_tx_2_G_p : out std_logic; -- Green
TMDS_tx_2_G_n : out std_logic;
TMDS_tx_1_R_p : out std_logic; -- Red
TMDS_tx_1_R_n : out std_logic;
TMDS_tx_0_B_p : out std_logic; -- Blue
TMDS_tx_0_B_n : out std_logic
);
end CharDispCtrlerTest_HDMI;
architecture RTL of CharDispCtrlerTest_HDMI is
component pixclk_gen
port (-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component CharDispCtrlerTest
generic(
ENABLE_COUNT : integer := 250000
);
port (
clk : in std_logic;
reset : in std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic;
display_enable : out std_logic
);
end component;
component dvi_disp
generic (
PLL_CLKFBOUT_MULT : integer := 20; -- VGA解像度 PLL VCO Freq 400MHz ~ 1000MHz
PLL_CLKIN_PERIOD : real := 40.0; -- VGA ピクセルクロック周期
PLL_CLKOUT0_DIVIDE : integer := 2; -- ピクセルクロックX10
PLL_CLKOUT1_DIVIDE : integer := 20; -- ピクセルクロック
PLL_CLKOUT2_DIVIDE : integer := 10 -- ピクセルクロックX2
);
port (
pixclk : in std_logic; -- pixel clock
reset_in : in std_logic; -- active high
red_in : in std_logic_vector(7 downto 0); -- RED入力
green_in : in std_logic_vector(7 downto 0); -- GREEN入力
blue_in : in std_logic_vector(7 downto 0); -- BLUE入力
hsync : in std_logic;
vsync : in std_logic;
display_enable : in std_logic; -- 表示が有効
TMDS_tx_clk_p : out std_logic; -- Clock
TMDS_tx_clk_n : out std_logic;
TMDS_tx_2_G_p : out std_logic; -- Green
TMDS_tx_2_G_n : out std_logic;
TMDS_tx_1_R_p : out std_logic; -- Red
TMDS_tx_1_R_n : out std_logic;
TMDS_tx_0_B_p : out std_logic; -- Blue
TMDS_tx_0_B_n : out std_logic
);
end component;
signal clk_100 : std_logic;
signal pixclk : std_logic;
signal reset : std_logic;
signal locked : std_logic;
signal vga_red, vga_green, vga_blue : std_logic;
signal vga_hsync, vga_vsync : std_logic;
signal display_enable : std_logic;
signal vga_r8, vga_g8, vga_b8 : std_logic_vector(7 downto 0);
begin
pixclk_gen_inst : pixclk_gen port map (
CLK_IN1 => sysclk,
CLK_OUT1 => clk_100,
CLK_OUT2 => pixclk,
RESET => reset_sw,
LOCKED => locked
);
reset <= not locked;
CharDispCtrlerTest_inst : CharDispCtrlerTest generic map (
ENABLE_COUNT => ENABLE_COUNT
) port map (
clk => pixclk,
reset => reset,
VGA_RED => vga_red,
VGA_GREEN => vga_green,
VGA_BLUE => vga_blue,
VGA_HSYNC => vga_hsync,
VGA_VSYNC => vga_vsync,
display_enable => display_enable
);
vga_r8 <= x"FF" when VGA_RED='1' else x"00";
vga_g8 <= x"FF" when VGA_GREEN='1' else x"00";
vga_b8 <= x"FF" when VGA_BLUE='1' else x"00";
-- VGA解像度 PLL VCO Freq=400MHz ~ 1000MHz なので、25MHz入力クロックだと最初に20倍する必要がある。
dvi_disp_inst : dvi_disp generic map (
PLL_CLKFBOUT_MULT => 20,
PLL_CLKIN_PERIOD => 40.0,
PLL_CLKOUT0_DIVIDE => 2,
PLL_CLKOUT1_DIVIDE => 20,
PLL_CLKOUT2_DIVIDE => 10
) port map (
pixclk => pixclk,
reset_in => reset,
red_in => vga_r8,
green_in => vga_g8,
blue_in => vga_b8,
hsync => vga_hsync,
vsync => vga_vsync,
display_enable => display_enable,
TMDS_tx_clk_p => TMDS_tx_clk_p,
TMDS_tx_clk_n => TMDS_tx_clk_n,
TMDS_tx_2_G_p => TMDS_tx_2_G_p,
TMDS_tx_2_G_n => TMDS_tx_2_G_n,
TMDS_tx_1_R_p => TMDS_tx_1_R_p,
TMDS_tx_1_R_n => TMDS_tx_1_R_n,
TMDS_tx_0_B_p => TMDS_tx_0_B_p,
TMDS_tx_0_B_n => TMDS_tx_0_B_n
);
end RTL;
NET "sysclk" LOC = L15;
NET "reset_sw" LOC = P3;
# Blue
NET "TMDS_tx_0_B_p" IOSTANDARD = TMDS_33;
NET "TMDS_tx_0_B_p" LOC = D8;
NET "TMDS_tx_0_B_n" IOSTANDARD = TMDS_33;
NET "TMDS_tx_0_B_n" LOC = C8;
# Red
NET "TMDS_tx_1_R_p" IOSTANDARD = TMDS_33;
NET "TMDS_tx_1_R_p" LOC = C7;
NET "TMDS_tx_1_R_n" IOSTANDARD = TMDS_33;
NET "TMDS_tx_1_R_n" LOC = A7;
# Green
NET "TMDS_tx_2_G_p" IOSTANDARD = TMDS_33;
NET "TMDS_tx_2_G_p" LOC = B8;
NET "TMDS_tx_2_G_n" IOSTANDARD = TMDS_33;
NET "TMDS_tx_2_G_n" LOC = A8;
# Clock
NET "TMDS_tx_clk_p" IOSTANDARD = TMDS_33;
NET "TMDS_tx_clk_p" LOC = B6;
NET "TMDS_tx_clk_n" IOSTANDARD = TMDS_33;
NET "TMDS_tx_clk_n" LOC = A6;
NET "sysclk" TNM_NET = "TNM_SYSCLK";
TIMESPEC TS_SYSCLK = PERIOD "TNM_SYSCLK" 100 MHz HIGH 50 % PRIORITY 0;
# PlanAhead Generated IO constraints
NET "reset_sw" IOSTANDARD = LVCMOS18;
NET "sysclk" IOSTANDARD = LVCMOS33;
// dvi_disp.v
// DVI表示ユニット
//
`default_nettype none
module dvi_disp #(
parameter PLL_CLKFBOUT_MULT = 20, // VGA解像度 PLL VCO Freq=400MHz ~ 1000MHz
parameter PLL_CLKIN_PERIOD = 40.0, // VGA ピクセルクロック周期
parameter PLL_CLKOUT0_DIVIDE = 2, // ピクセルクロックX10
parameter PLL_CLKOUT1_DIVIDE = 20, // ピクセルクロック
parameter PLL_CLKOUT2_DIVIDE = 10) // ピクセルクロックX2
(
input wire pixclk, // pixel clock
input wire reset_in, // active high
input wire [7:0] red_in, // RED入力
input wire [7:0] green_in, // GREEN入力
input wire [7:0] blue_in, // BLUE入力
input wire hsync,
input wire vsync,
input wire display_enable, // 表示が有効
output wire TMDS_tx_clk_p, // Clock
output wire TMDS_tx_clk_n,
output wire TMDS_tx_2_G_p, // Green
output wire TMDS_tx_2_G_n,
output wire TMDS_tx_1_R_p, // Red
output wire TMDS_tx_1_R_n,
output wire TMDS_tx_0_B_p, // Blue
output wire TMDS_tx_0_B_n
);
// CharDispCtrlerTest_HDMI.v
// CharDispCtrlerTest.vのHDMI用のラッパー、HDMIコネクタから出力する
`default_nettype none
module CharDispCtrlerTest_HDMI (
input wire sysclk,
input wire reset_sw,
output wire TMDS_tx_clk_p, // Clock
output wire TMDS_tx_clk_n,
output wire TMDS_tx_2_G_p, // Green
output wire TMDS_tx_2_G_n,
output wire TMDS_tx_1_R_p, // Red
output wire TMDS_tx_1_R_n,
output wire TMDS_tx_0_B_p, // Blue
output wire TMDS_tx_0_B_n
);
wire clk_100;
wire pixclk;
wire reset;
wire locked;
wire vga_red, vga_green, vga_blue;
wire vga_hsync, vga_vsync;
wire display_enable;
pixclk_gen pixclk_gen_inst
(// Clock in ports
.CLK_IN1(sysclk), // IN
// Clock out ports
.CLK_OUT1(clk_100), // OUT
.CLK_OUT2(pixclk), // OUT
// Status and control signals
.RESET(reset_sw),// IN
.LOCKED(locked) // OUT
);
assign reset = !locked;
CharDispCtrlerTest CharDispCtrlerTest_inst (
.clk(pixclk),
.reset(reset),
.VGA_RED(vga_red), // 1bit
.VGA_GREEN(vga_green), // 1bit
.VGA_BLUE(vga_blue), // 1bit
.VGA_HSYNC(vga_hsync),
.VGA_VSYNC(vga_vsync),
.display_enable(display_enable)
);
// VGA解像度 PLL VCO Freq=400MHz ~ 1000MHz なので、25MHz入力クロックだと最初に20倍する必要がある。
dvi_disp #(
.PLL_CLKFBOUT_MULT(20),
.PLL_CLKIN_PERIOD(40.0),
.PLL_CLKOUT0_DIVIDE(2),
.PLL_CLKOUT1_DIVIDE(20),
.PLL_CLKOUT2_DIVIDE(10))
dvi_disp_inst (
.pixclk(pixclk),
.reset_in(reset),
.red_in({8{vga_red}}),
.green_in({8{vga_green}}),
.blue_in({8{vga_blue}}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.display_enable(display_enable),
.TMDS_tx_clk_p(TMDS_tx_clk_p),
.TMDS_tx_clk_n(TMDS_tx_clk_n),
.TMDS_tx_2_G_p(TMDS_tx_2_G_p),
.TMDS_tx_2_G_n(TMDS_tx_2_G_n),
.TMDS_tx_1_R_p(TMDS_tx_1_R_p),
.TMDS_tx_1_R_n(TMDS_tx_1_R_n),
.TMDS_tx_0_B_p(TMDS_tx_0_B_p),
.TMDS_tx_0_B_n(TMDS_tx_0_B_n)
);
endmodule
`default_nettype wire
module CharDispCtrlerTest_HDMI_tb;
// Inputs
reg sysclk;
reg reset_sw;
// Outputs
wire TMDS_tx_clk_p; // Clock
wire TMDS_tx_clk_n;
wire TMDS_tx_2_G_p; // Green
wire TMDS_tx_2_G_n;
wire TMDS_tx_1_R_p; // Red
wire TMDS_tx_1_R_n;
wire TMDS_tx_0_B_p; // Blue
wire TMDS_tx_0_B_n;
// Instantiate the Unit Under Test (UUT)
CharDispCtrlerTest_HDMI uut (
.sysclk(sysclk),
.reset_sw(reset_sw),
.TMDS_tx_clk_p(TMDS_tx_clk_p),
.TMDS_tx_clk_n(TMDS_tx_clk_n),
.TMDS_tx_2_G_p(TMDS_tx_2_G_p),
.TMDS_tx_2_G_n(TMDS_tx_2_G_n),
.TMDS_tx_1_R_p(TMDS_tx_1_R_p),
.TMDS_tx_1_R_n(TMDS_tx_1_R_n),
.TMDS_tx_0_B_p(TMDS_tx_0_B_p),
.TMDS_tx_0_B_n(TMDS_tx_0_B_n)
);
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
sysclk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) sysclk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
// Instantiate the Unit Under Test (UUT)
defparam uut.CharDispCtrlerTest_inst.ENABLE_COUNT = 23'd000004; // シミュレーション
initial begin
// Initialize Inputs
reset_sw = 1'b1;
// Wait 100 ns for global reset to finish
#100;
reset_sw = 1'b0;
// Add stimulus here
#20000000 $stop;
end
endmodule
// dvi_disp.v
// DVI表示ユニット
//
`default_nettype none
module dvi_disp #(parameter CLKIN_PERIOD = 40.0) // VGA解像度
(
input wire pixclk, // pixel clock
input wire reset_in, // active high
input wire [7:0] red_in, // RED入力
input wire [7:0] green_in, // GREEN入力
input wire [7:0] blue_in, // BLUE入力
input wire hsync,
input wire vsync,
input wire display_enable, // 表示が有効
output wire [3:0] TMDS,
output wire [3:0] TMDSB
);
// CharDispCtrlerTest_HDMI.v
// CharDispCtrlerTest.vのHDMI用のラッパー、HDMIコネクタから出力する
`default_nettype none
module CharDispCtrlerTest_HDMI (
input wire sysclk,
input wire reset_sw,
output wire [3:0] TMDS,
output wire [3:0] TMDSB
);
wire clk_100;
wire pixclk;
wire reset;
wire locked;
wire vga_red, vga_green, vga_blue;
wire vga_hsync, vga_vsync;
wire display_enable;
pixclk_gen pixclk_gen_inst
(// Clock in ports
.CLK_IN1(sysclk), // IN
// Clock out ports
.CLK_OUT1(clk_100), // OUT
.CLK_OUT2(pixclk), // OUT
// Status and control signals
.RESET(reset_sw),// IN
.LOCKED(locked) // OUT
);
assign reset = !locked;
CharDispCtrlerTest CharDispCtrlerTest_inst (
.clk(pixclk),
.reset(reset),
.VGA_RED(vga_red), // 1bit
.VGA_GREEN(vga_green), // 1bit
.VGA_BLUE(vga_blue), // 1bit
.VGA_HSYNC(vga_hsync),
.VGA_VSYNC(vga_vsync),
.display_enable(display_enable)
);
dvi_disp #(
.CLKIN_PERIOD(40.0))
dvi_disp_inst (
.pixclk(pixclk),
.reset_in(reset),
.red_in({8{vga_red}}),
.green_in({8{vga_green}}),
.blue_in({8{vga_blue}}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.display_enable(display_enable),
.TMDS(TMDS),
.TMDSB(TMDSB)
);
endmodule
`default_nettype wire
module CharDispCtrlerTest_HDMI_tb;
// Inputs
reg sysclk;
reg reset_sw;
// Outputs
wire [3:0] TMDS;
wire [3:0] TMDSB;
// Instantiate the Unit Under Test (UUT)
CharDispCtrlerTest_HDMI uut (
.sysclk(sysclk),
.reset_sw(reset_sw),
.TMDS(TMDS),
.TMDSB(TMDSB)
);
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
sysclk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) sysclk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
// Instantiate the Unit Under Test (UUT)
defparam uut.CharDispCtrlerTest_inst.ENABLE_COUNT = 23'd000004; // シミュレーション
initial begin
// Initialize Inputs
reset_sw = 1'b1;
// Wait 100 ns for global reset to finish
#100;
reset_sw = 1'b0;
// Add stimulus here
#20000000 $stop;
end
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:06:11 02/15/2012
// Design Name: vtc_demo
// Module Name: H:/HDL/FndtnISEWork/Spartan6/Atlys/xapp495/dvi_demo/vtc_demo/vtc_deom_tb.v
// Project Name: vtc_demo
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: vtc_demo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module vtc_deom_tb;
// Inputs
reg RSTBTN;
reg SYS_CLK;
reg [3:0] SW;
// Outputs
wire [3:0] TMDS;
wire [3:0] TMDSB;
wire [3:0] LED;
wire [1:0] DEBUG;
// Instantiate the Unit Under Test (UUT)
vtc_demo uut (
.RSTBTN(RSTBTN),
.SYS_CLK(SYS_CLK),
.SW(SW),
.TMDS(TMDS),
.TMDSB(TMDSB),
.LED(LED),
.DEBUG(DEBUG)
);
parameter PERIOD = 10; // 100MHz clock
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for SYS_CLK
begin
SYS_CLK = 1'b0;
#OFFSET;
forever begin
SYS_CLK = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) SYS_CLK = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Initialize Inputs
RSTBTN = 1'b1;
SW = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
RSTBTN = 1'b0;
end
endmodule
NET "LED<0>" LOC = "U18";
NET "LED<1>" LOC = "M14";
NET "LED<2>" LOC = "N14";
NET "LED<3>" LOC = "L14";
・出力の信号線は4本で、R, G, Bとクロックがある。信号規格はTMDSで差動信号となっている。
・出力する信号はRGB 4:4:4がデフォルトで、YCrCb 4:4:4 and YCrCb 4:2:2にも対応する。
・R, G, Bそれぞれ8ビット幅でそれを8B10Bで10ビットにエンコードする。
・10ビットデータを10：1のシアライザでシリアルデータにして、ピクセルクロックの10倍で伝送する。
・HDMIの場合は音声信号もあるので、4ビットのAUX0, AUX1, AUX2 が入る。これは、R, G, Bの映像信号の代わりに送られる。
・映像信号のブランキングの間は4種類のコントロール・トークンが送られる。
・コントロール・トークンには、video line scan (HSYNC) や frame update (VSYNC) information がある。
・HDMIは映像のブランキングの間、映像信号の代わりにオーディオ信号 (AUX0, AUX1, AUX2) を送るが、DVIは送らないということだ。
・ブランキングの時に2ビットのコントロール信号を送る。
・エンコーダーはR, G, Bの8B10Bエンコーダ、オーディオ信号の4B10Bエンコーダ、ブランキング時のコントロール信号用に2B10Bエンコーダが必要となる。
//
// Atlys_LED_int.c
//
// AltysボードのLEDを1秒ごとに+1するソフトウェア
// FITの割り込みを使用する
//
#define GPO1_ADDR 0x80000010
#define GPI1_ADDR 0x80000020
#define IRQ_ENABLE 0x80000038
#define IRQ_ACK 0x8000003C
#define FIT1_INTERRUPT_BIT 0x80 // FIT1の割り込みビット位置
volatile int interrupt = 0;
//割り込み処理
void interrupt_handler() __attribute__ ((interrupt_handler));
void interrupt_handler() {
interrupt = 1;
*(volatile unsigned int *)(IRQ_ACK) = FIT1_INTERRUPT_BIT;
}
//割り込み許可
void microblaze_enable_interrupts()
{
__asm__(
"mfs r12, rmsr\n\t" //Read the MSR register
"ori r12, r12, 2\n\t" //Set the interrupt enable bit
"mts rmsr, r12\n\t" //Save the MSR register
);
}
//割り込み禁止
void microblaze_disable_interrupts()
{
__asm__(
"mfs r12, rmsr\n\t" //Read the MSR register
"andi r12, r12, ~2\n\t" //Clear the interrupt enable bit
"mts rmsr, r12\n\t" //Save the MSR register
);
}
int main()
{
unsigned int led = 0x55;
*(volatile unsigned int *)(GPO1_ADDR) = led;
microblaze_enable_interrupts();
*(volatile unsigned int *)(IRQ_ENABLE) = FIT1_INTERRUPT_BIT;
while(1){
// FIT割り込み待ち
interrupt = 0;
while(interrupt==0);
*(volatile unsigned int *)(GPO1_ADDR) = led++;
}
}
TARGET=Atlys_LED_int.elf
TARGET_DEBUG=Atlys_LED_int_debug.elf
SRCDIR=./
OBJDIR=./
SRCS= $(SRCDIR)Atlys_LED_int.c
OBJS= $(OBJDIR)Atlys_LED_int.o
OBJS_DEBUG= $(OBJDIR)Atlys_LED_int_debug.o
CC=mb-gcc
CFLAGS=-O2 -mlittle-endian -Wl,-Map=Atlys_LED_int.map
CFLAGS_DEBUG=-O0 -g -mlittle-endian -Wl,-Map=Atlys_LED_int_debug.map
LDFLAGS1=-Wl,-s
$(TARGET) : $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS1) $(OBJS) -o $(OBJDIR)$(TARGET) $(LDFLAGS2)
$(OBJDIR)Atlys_LED_int.o: $(SRCDIR)Atlys_LED_int.c $(INCS)
$(CC) $(CFLAGS) -c $< -o $@
clean:
rm -f $(OBJDIR)*.elf $(OBJDIR)*.o $(OBJDIR)*.map
debug: $(TARGET_DEBUG)
$(TARGET_DEBUG) : $(OBJS_DEBUG)
$(CC) $(CFLAGS_DEBUG) $(OBJS_DEBUG) -o $(OBJDIR)$(TARGET_DEBUG) $(LDFLAGS2)
$(OBJDIR)Atlys_LED_int_debug.o: $(SRCDIR)Atlys_LED_int.c $(INCS)
$(CC) $(CFLAGS_DEBUG) -c $< -o $@
TARGET=Atlys_LED_test.elf
TARGET_DEBUG=Atlys_LED_test_debug.elf
SRCDIR=./
OBJDIR=./
SRCS= $(SRCDIR)Atlys_LED_test.c
OBJS= $(OBJDIR)Atlys_LED_test.o
OBJS_DEBUG= $(OBJDIR)Atlys_LED_test_debug.o
CC=mb-gcc
CFLAGS=-O2 -mlittle-endian -Wl,-Map=Atlys_LED_test.map
CFLAGS_DEBUG=-O0 -g -mlittle-endian -Wl,-Map=Atlys_LED_test_debug.map
LDFLAGS1=-Wl,-s
$(TARGET) : $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS1) $(OBJS) -o $(OBJDIR)$(TARGET) $(LDFLAGS2)
$(OBJDIR)Atlys_LED_test.o: $(SRCDIR)Atlys_LED_test.c $(INCS)
$(CC) $(CFLAGS) -c $< -o $@
clean:
rm -f $(OBJDIR)*.elf $(OBJDIR)*.o $(OBJDIR)*.map
debug: $(TARGET_DEBUG)
$(TARGET_DEBUG) : $(OBJS_DEBUG)
$(CC) $(CFLAGS_DEBUG) $(OBJS_DEBUG) -o $(OBJDIR)$(TARGET_DEBUG) $(LDFLAGS2)
$(OBJDIR)Atlys_LED_test_debug.o: $(SRCDIR)Atlys_LED_test.c $(INCS)
$(CC) $(CFLAGS_DEBUG) -c $< -o $@
//
// Atlys_LED_test.c
//
// AltysボードのLEDを1秒ごとに+1するソフトウェア
// 初めは割り込みを使わないで実行する
//
#define GPO1_ADDR 0x80000010
#define GPI1_ADDR 0x80000020
#define PIT1_PRELOAD_ADDR 0x80000040
#define PIT1_COUNTER_ADDR 0x80000044
#define PIT1_CONTROL_ADDR 0x80000048
#define COUNT_VALUE 100
int main()
{
unsigned int b_GPI1 = 0;
unsigned int c_GPI1 = 0;
unsigned int led = 0x55;
*(volatile unsigned int *)(PIT1_PRELOAD_ADDR) = COUNT_VALUE; // 100MHzで1秒
*(volatile unsigned int *)(PIT1_CONTROL_ADDR) = 0x3; // Timer Enable, Auto Reload
*(volatile unsigned int *)(GPO1_ADDR) = led;
while(1){
c_GPI1 = 0x2 & (*(volatile unsigned int *)(GPI1_ADDR));
if (c_GPI1 != b_GPI1){
*(volatile unsigned int *)(GPO1_ADDR) = led++;
}
b_GPI1 = c_GPI1;
}
}
# PROJECT: Build New MicroBlaze
# ----------------------------------------------------------------------
#
# Copyright (C) 2011-2012 H.Ishihara, http://www.aquaxis.com/
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files (the
# "Software"), to deal in the Software without restriction, including
# without limitation the rights to use, copy, modify, merge, publish,
# distribute, sublicense, and/or sell copies of the Software, and to
# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
# LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
# OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
# WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
# For further information please contact.
# http://www.aquaxis.com/
# info(at)aquaxis.com or hidemi(at)sweetcafe.jp
TARGET=Atlys_LED_test.elf
SRCDIR=./
OBJDIR=./
SRCS= $(SRCDIR)Atlys_LED_test.c
OBJS= $(OBJDIR)Atlys_LED_test.o
CC=mb-gcc
CFLAGS=-O2 -mlittle-endian -Wl,-Map=Atlys_LED_test.map
LDFLAGS1=-Wl,-s
$(TARGET) : $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS1) $(OBJS) -o $(OBJDIR)$(TARGET) $(LDFLAGS2)
$(OBJDIR)Atlys_LED_test.o: $(SRCDIR)Atlys_LED_test.c $(INCS)
$(CC) $(CFLAGS) -c $< -o $@
clean:
rm -f Atlys_LED_test.elf $(OBJDIR)*.o Atlys_LED_test.map
//
// Atlys_LED_test.c
//
// AltysボードのLEDを1秒ごとに+1するソフトウェア
// 初めは割り込みを使わないで実行する
//
#define GPO1_ADDR 0x80000010
#define GPI1_ADDR 0x80000020
#define PIT1_PRELOAD_ADDR 0x80000040
#define PIT1_COUNTER_ADDR 0x80000044
#define PIT1_CONTROL_ADDR 0x80000048
#define COUNT_VALUE 100
int main()
{
unsigned int b_GPI1 = 0;
unsigned int c_GPI1 = 0;
unsigned int led = 0x55;
*(volatile unsigned int *)(PIT1_PRELOAD_ADDR) = COUNT_VALUE; // 100MHzで1秒
*(volatile unsigned int *)(PIT1_CONTROL_ADDR) = 0x3; // Timer Enable, Auto Reload
*(volatile unsigned int *)(GPO1_ADDR) = led;
while(1){
c_GPI1 = 0x2 & (*(volatile unsigned int *)(GPI1_ADDR));
if (c_GPI1 != b_GPI1){
*(volatile unsigned int *)(GPO1_ADDR) = led++;
}
b_GPI1 = c_GPI1;
}
}
module MicroBlaze_MCS_Test(
input wire clk,
input wire reset,
// input wire UART_Rx,
// output wire UART_Tx,
output wire [7:0] LED_out
);
wire PIT1_Interrupt;
wire PIT1_Toggle;
wire INTC_IRQ;
wire [7:0] GPI1;
wire FIT1_Interrupt;
wire FIT1_Toggle;
assign GPI1 = {6'd0, FIT1_Toggle, PIT1_Toggle};
MB_MCS mcs_0 (
.Clk(clk), // input Clk
.Reset(reset), // input Reset
// .UART_Rx(UART_Rx), // input UART_Rx
// .UART_Tx(UART_Tx), // output UART_Tx
.FIT1_Interrupt(FIT1_Interrupt), // output FIT1_Interrupt
.FIT1_Toggle(FIT1_Toggle), // output FIT1_Toggle
.PIT1_Enable(1'b1), // input PIT1_Enable
.PIT1_Interrupt(PIT1_Interrupt), // output PIT1_Interrupt
.PIT1_Toggle(PIT1_Toggle), // output PIT1_Toggle
.GPO1(LED_out), // output [7 : 0] GPO1
.GPI1(GPI1), // input [7 : 0] GPI1
.INTC_IRQ(INTC_IRQ) // output INTC_IRQ
);
endmodule
#define GPO1_ADDR 0x80000010
#define GPI1_ADDR 0x80000020
#define COUNT_VALUE 100
int main()
{
unsigned int b_GPI1 = 0;
unsigned int c_GPI1 = 0;
unsigned int led = 0x55;
*(volatile unsigned int *)(GPO1_ADDR) = led;
while(1){
c_GPI1 = 0x2 & (*(volatile unsigned int *)(GPI1_ADDR));
if (c_GPI1 != b_GPI1){
*(volatile unsigned int *)(GPO1_ADDR) = led++;
}
b_GPI1 = c_GPI1;
}
}
source ipcore_dir/microblaze_mcs_setup.tcl
microblaze_mcs_data2mem SDK/Atlys_LED_Test/Debug/Atlys_LED_Test.elf
//
// Atlys_LED_test.c
//
// AltysボードのLEDを1秒ごとに+1するソフトウェア
// 初めは割り込みを使わないで実行する
//
#define GPIO1_ADDR 0x80000010
#define PIT1_PRELOAD_ADDR 0x80000040
#define PIT1_COUNTER_ADDR 0x80000044
#define PIT1_CONTROL_ADDR 0x80000048
unsigned int read_counter(){
return(*(volatile unsigned int *)(PIT1_COUNTER_ADDR));
}
int main()
{
unsigned int b_count = 0;
unsigned int c_count = 0;
unsigned int led = 0x55;
*(volatile unsigned int *)(PIT1_PRELOAD_ADDR) = 10; // 100MHzで1秒
*(volatile unsigned int *)(PIT1_CONTROL_ADDR) = 0x3; // Timer Enable, Auto load
*(volatile unsigned int *)(GPIO1_ADDR) = led;
while(1){
c_count = read_counter();
*(volatile unsigned int *)(GPIO1_ADDR) = c_count;
if (c_count > b_count){ // 現在の値のほうが大きいのでオートロードした
*(volatile unsigned int *)(GPIO1_ADDR) = led++;
}
*(volatile unsigned int *)(GPIO1_ADDR) = led++;
b_count = c_count;
}
}
module MicroBlaze_MCS_Test(
input wire clk,
input wire reset,
output wire [7:0] LED_out
);
wire PIT1_Interrupt;
wire PIT1_Toggle;
wire INTC_IRQ;
assign reset_n = ! reset;
MB_MCS mcs_0 (
.Clk(clk), // input Clk
.Reset(reset), // input Reset
.PIT1_Enable(1'b1), // input PIT1_Enable
.PIT1_Interrupt(PIT1_Interrupt), // output PIT1_Interrupt
.PIT1_Toggle(PIT1_Toggle), // output PIT1_Toggle
.GPO1(LED_out), // output [7 : 0] GPO1
.INTC_IRQ(INTC_IRQ) // output INTC_IRQ
);
endmodule
`timescale 1ns / 1ps
module MicroBlaze_MCS_Test_tb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [7:0] LED_out;
// Instantiate the Unit Under Test (UUT)
MicroBlaze_MCS_Test uut (
.clk(clk),
.reset(reset),
.LED_out(LED_out)
);
parameter PERIOD = 10; // 100MHz clock
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
clk = 1'b0;
#OFFSET;
forever begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Initialize Inputs
reset = 1'b1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1'b0;
end
endmodule
NET "LED_out[0]" LOC = U18;
NET "LED_out[1]" LOC = M14;
NET "LED_out[2]" LOC = N14;
NET "LED_out[3]" LOC = L14;
NET "LED_out[4]" LOC = M13;
NET "LED_out[5]" LOC = D4;
NET "LED_out[6]" LOC = P16;
NET "LED_out[7]" LOC = N12;
NET "clk" LOC = L15;
NET "reset" LOC = P3;
NET "LED_out[0]" IOSTANDARD = LVCMOS33;
NET "LED_out[1]" IOSTANDARD = LVCMOS33;
NET "LED_out[2]" IOSTANDARD = LVCMOS33;
NET "LED_out[3]" IOSTANDARD = LVCMOS33;
NET "LED_out[4]" IOSTANDARD = LVCMOS33;
NET "LED_out[5]" IOSTANDARD = LVCMOS33;
NET "LED_out[6]" IOSTANDARD = LVCMOS33;
NET "clk" IOSTANDARD = LVCMOS33;
NET "reset" IOSTANDARD = LVCMOS18;
NET "clk" TNM_NET = "clk";
TIMESPEC TS_sysclk = PERIOD "clk" 10 ns HIGH 50 %;
| 日 | 月 | 火 | 水 | 木 | 金 | 土 |
|---|---|---|---|---|---|---|
| - | - | - | 1 | 2 | 3 | 4 |
| 5 | 6 | 7 | 8 | 9 | 10 | 11 |
| 12 | 13 | 14 | 15 | 16 | 17 | 18 |
| 19 | 20 | 21 | 22 | 23 | 24 | 25 |
| 26 | 27 | 28 | 29 | - | - | - |