Browser Not SupportedArchitecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse | IEEE Conference Publication | IEEE Xplore

Notice: IEEE Xplore is unable to display this page because you may be using an incompatible or unsupported browser.

For the best experience, please upgrade to a newer, supported browser using the links below. If you cannot upgrade your browser, a temporary IEEE Xplore site is available for basic searches with links to full-text.