Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

Wireless power transfer requires multilevel energy conversion for energy transfer, resulting in a bulky system. This paper proposes a direct AC-AC converter topology denoted as double half-bridge series-matrix converter and introduces a symmetric modulation method that eliminates the need for input voltage polarity detection. The converter circumvents DC conversion and operates at a unit power factor without the assistance of power factor correction. A 1kw prototype was constructed and the same control strategy was adopted, without considering the polarity or magnitude of the input voltage, verifying the accuracy and reliability of the proposed topology. The transmission efficiency was achieved at 91.43%.

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000∼100000 LUTs comparing with existing methods, with full fault coverage.

In this paper, an improved coverage optimization method for video sensor networks(VSNs) based on Whale optimization algorithm (SGWOA) is proposed to solve the problem of uneven distribution of nodes in random deployment of video sensor networks, which will cause coverage holes or coverage redundancy in the coverage area of VSNs. Firstly, Sobol sequence is used to initialize the population, which improves the diversity of the population and makes the distribution of network nodes more uniform when randomly deployed. Secondly, the nonlinear convergence factor and adaptive inertia weight are introduced to prevent the algorithm from falling into local optimal prematurely. Finally, Levi's flight strategy is added to disturb the position update during whale optimization, which speeds up the convergence of the algorithm and avoids premature convergence.

This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

Swimming is one of the most popular worldwide sports, which offers the players healthy body, improved fitness, and endless enjoyment due to its easy accessibility and year-round availability. Monitoring swimmers can aid in the development and participation of swimming sport. However, due to the difficulty of in-water monitoring, the existing methods in tool box are still limited. In this paper, a more accessible wearable monitoring system based on a flexible piezoelectric device is developed. This system collects muscle contracting and relaxing information by measuring its generated force on a Polyvinylidene fluoride (PVDF) sensor. Then the information is transmitted via a low-frequency radio frequency (RF) signal to the receiver on land. This information is analyzed using a convolutional neural network and the classification of different strokes is realized. The system also supports monitoring at two positions by wearing multiple devices on the body. By integrating data from multiple positions, the analysis algorithm achieves a higher prediction accuracy of over 95%. This work demonstrates that the combination of wearable monitoring devices, the Internet of Things, and Artificial Intelligence, which holds significant promise for sports education, research, promotion, and development.

This study develops new technology for detecting metal foreign objects to enhance the safety of wireless charging systems. The intrusion of metal objects during charging may result in reduced performance, increased energy consumption, and excessive heat generation, which may potentially damage the charging system. In this paper, we develop an innovative sensorless method of detecting foreign objects. We build an efficiency model by conducting experiments with metal objects of various sizes placed between charging coils. This approach identifies metal objects on the basis of efficiency changes, eliminating the need for sensors, thus effectively reducing costs. Finally, the effectiveness and reliability of this model are validated using the experimental platform.

This paper presents a transparent super-wideband (SWB) MIMO antenna based on a metal mesh structure. The metal patch and substrate of the antenna are hollowed out, resulting in a transparency of up to 77% and a radiation efficiency exceeding 82%. The bandwidth of this MIMO antenna ranges from 1.6 to 19.2 GHz, achieving a bandwidth ratio of 12: 1. An engineered parasitic decoupling structure ensures that the isolation between antenna elements is greater than 25 dB, and the envelope correlation coefficient (ECC), diversity gain (DG), channel capacity loss (CCL), and total active reflection coefficient (TARC) all reach good values.

This paper proposes a voltage-controllable switched reluctance generator (SRG) system with a ring winding structure driven by a full-bridge power converter, which is the first application of a full-bridge power converter to drive the SRG. The proposed topology inherits the advantage of low copper loss of the ring winding that combines AC and DC currents together. It connects the equivalent DC power provided by a DC-DC half-bridge circuit to the ring winding to provide circulating DC and partial excitation energy. This paper provides a detailed description of the proposed system's feedback loops and operating principle. The proposed topology is compared with the uncontrollable Circulating-Current-Excited Switched Reluctance Generator (CCEG). The comparative study is validated through simulation and experimental platform, and the results highlight the output voltage performance of the proposed topology and control method.

This article proposes a constant current regulation design for pri­mary-side controlled flyback converter. The regulation circuit consists of two parts: an OSC circuit and an adaptive primary side peak current thresh­old compensation circuit. The OSC circuit generates a switching cycle sig­nal with a fixed ratio to the demagnetization time, and the adaptive primary side peak current threshold compensation circuit. To verify the feasibility and accuracy of the proposed constant current regulation design, the de­signed chip was fabricated and tested. Under 12V/1.9A configuration, the test results showed that the line regulation and load regulation of the output current can achieve within ±1.7% and ±0.15%, respectively.

In this work, gate leakage behavior on Schottky-type p-GaN gate AlGaN/GaN HEMT is investigated, especially when the Schottky junction is damaged. A controllable degradation of the Schottky junction is achieved, then the previous semi-floated p-GaN is electrically connected to the gate electrode. Therefore, the pre-stressed GaN device exhibits an improved gate stability, as well as a normal gate control and large gate swing. Furthermore, the associated trap level is extracted by Arrhenius plot based on the exponential relationship between the recovery speed versus temperature.

While CNT FETs have been demonstrated to exhibit excellent resistance to irradiation, the radiation effects in complex environments remain relatively understudied. This paper investigates the synergistic effect of CNT FETs under the combined action of ionization and displacement damage using proton irradiation. It was observed that the V_th degradation (0.06 V) induced by 40 MeV protons was twice that (0.03 V) induced by 70 MeV protons with the same ionization dose. The numerical simulations indicated that the 40 MeV proton irradiation results in the formation of displacement defects in closer proximity to the semiconductor channel. This increased the hole capture rate, leading to a higher concentration of fixed charge in the SiO₂ layer and a larger threshold voltage shift.

A pulse stretch interpolator used in low-cost and low-power CMOS time-to-digital converter (TDC) is proposed in this paper. The reference clock frequency of the TDC is 6.4 MHz and the range is 5120 us. The chip size is 0.5 mm x 0.5 mm as fabricated in the TSMC 180nm CMOS process. The time resolution can be realized as 10ps and the power consumption is 1.92 mW. The time period of an input is divided into two parts. The first step of coarse quantization uses a clock to quantize an integer number of clock cycles. The second step of fine quantization is to stretch the pulse width of less than one clock cycle after coarse quantization. The pulse stretch interpolator charges and discharges the capacitor under narrow input pulse control in order to expand the narrow pulse. In this way, TDC achieves higher resolution with low power consumption. The pulse stretch interpolator’s resolution is 1.55ps in all corners.

This brief presents a 0.18-μm BCD low-dropout regulator (LDO) designed for low-power Internet of Things (IoT) devices that achieves fast transient responses with a nA-level quiescent current (IQ) and operates without external capacitors. The power supply voltage can be reduced to 0.9 V, consuming only 284 nA of quiescent current. The design incorporates an adaptive bias and a class-AB OTA with dual Gm stages, achieving low IQ. Its second stage forms a feedforward path, utilizing only a 2 pF compensation capacitor. The combination of this feedforward path and an FVF buffer with body bias modulation enables zero-point load tracking compensation technology, ensuring loop stability under light loads in this capacitor-less LDO. Moreover, reducing the size of the pass transistor MP minimizes the overall area of the LDO to just 0.005 mm². An FVF buffer integrated with a comparator-based transient enhancement circuit improves the LDO's transient response. Post-simulation results demonstrate a load regulation of 0.0974 mV/mA, and a superior transient figure-of-merit (FOM) of 1.14-fs.

Latch-based resilient circuits significantly increases the area overhead to address short-path (SP) issues. This work presents a low-overhead resilient circuit with partial two-phase latch, which selectively inserts negative phase latches to resolve SP issues and reduces the number of insertion points. Furthermore, the monitoring paths reduction method is also proposed by leveraging the time-borrowing capability of latches. The proposed method is implemented on a RISC-V processor, achieving a performance enhancement of up to 73.7% and a power consumption reduction of up to 33%, with only a 6.5% area penalty.

This paper presents on the design, fabrication and test of a Schottky diode based mixer driving by a frequency doubler for solid-state receiver front-ends in the 380 GHz range. The 380 GHz sub-harmonic mixer has fabricated with the GaAs membrane process on a 3 μm-thick substrate suspended in a waveguide with metal beamleads, and exhibited an impressive double-side-band conversion loss of less than 10 dB in 1-23 GHz IF band with the optimal conversion loss of merely 6.4 dB. The 190 GHz frequency doubler based on Schottky diodes is the key in the local oscillator source and sufficiently pumps the mixer with 2∼5 mW of input power.

In digital DC-DC converter systems, factors such as noise, line mismatches, process variations between chips, and common mode level shifts can cause the overall system output voltage to deviate from expectations. This paper proposes a code-search-based accuracy calibration technique for the delay line based ADC in digital DC-DC converter system. By adjusting the calibration module and automatically searching for the maximum output code value, this technique effectively enhances the quantization accuracy of the ADC. The overall chip is fabricated using 0.18 μm CMOS technology, and the ADC occupies an area of 750 μm × 940 μm. Experiment results demonstrate that this technique can improve the ADC's quantization accuracy to 94.7% and reduce the overall DC-DC loop offset from 2.8% to 0.2%, significantly enhancing the accuracy of the DC-DC output.

This paper proposes a distributed secondary control strategy for heterogeneous battery energy storage systems (BESSs) in islanded microgrids, without requiring power measurements. The method uses local State-of-Charge (SoC) information to achieve energy balancing and proportional active power sharing by introducing distributed filters. Frequency and voltage regulation are also accomplished using local frequency and voltage information. The system stability under the proposed control strategy is rigorously proved based on the Lyapunov function method. Simulation is performed in the MATLAB/Simulink platform to verify the effectiveness of the proposed control method.

This letter proposes a novel design method for a resistive-resistive series of continuous modes (Res-Res SCMs) power amplifier (PA), which can extend the bandwidth of the SCMs PAs. With a waveform engineering method, we introduce the resistive part to the purely reactive second harmonic load of SCMs to overcome one-octave bandwidth limitation of traditional continuous PAs. The limitation is due to the inability to overlap between low-band and high-order harmonics and high-band fundamental waves. An ultra-wideband PA module across 0.4-3.1 GHz (154.3% bandwidth) is fabricated using a 10 W GaN HEMT device. The experimental results show a drain efficiency of 63%−81.7% can be achieved with a saturated output power of 38.6−42.3 dBm at 0.4-3.1 GHz.

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter's efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

This pretreating and decoding circuit is characterized by high speed and low area. This letter presents the shortest subsequence extraction algorithm as well as redefined and simplified methodology for character detection within single stage, eliminating redundant combinatorial logic and function block. Parallel 8B/10B decoder with mixed structure of decoding and disparity check is also proposed effectively. The circuit, acting as a significant role in JESD204B controller for Gigabit transmission, has been implemented and verified on Xilinx VC707 development kit. This design can achieve lane rate for up to 18.3Gbps, with increase in frequency by 31% and decrease in area by 12% compared with typical architecture and the optimization of the key components is also greatly remarkable.

In modern system on a chip (SoC), input/output (I/O) devices typically utilize direct memory access (DMA) and access virtual memory in the regular way. Additionally, operating system (OS) tends to allocate physical I/O memory contiguously. To reduce latency overhead due to page-table walks, hardware often employs translation lookaside buffer (TLB) prefetch techniques. Recently, TLB coalescing schemes that merge contiguous pages into a TLB entry have been reported. However, the conventional TLB prefetchers operate in the page level and do not effectively leverage the advantages of contiguous allocation. In this paper, we present the TLB prefetcher that exploits both contiguous allocation and TLB coalescing for I/O devices. The presented prefetcher operates in the block level, exploits contiguity in memory, requires no history tracking schemes, and can reduce page-table walks compared to the conventional scheme. Our experiments indicate that the presented scheme can improve both TLB and I/O device performance.

This paper discusses the complete absorption of microwaves by conductive plates and its application in heating technology. Numerical calculations were conducted to determine the conditions for complete absorption of 2.45 GHz microwaves propagating through a rectangular waveguide tube with an inner dimension of 5.5×10.9 cm². Based on the calculated results, we developed a resonating absorber with a three-layered structure of single-crystalline silicon (c-Si) which consisted of a 0.7-cm-thick semi-insulating c-Si substrate (DP) with a resistivity over 1000 Ωcm, a 0.49-cm-thick c-Si substrate (CP1) with 19-22 Ωcm, and a 0.05-cm-thick c-Si substrate (CP2) with 0.001 Ωcm or less. The absorber achieved complete microwave absorption with a measurement accuracy of 2%. Complete absorption was again observed when a half-wavelength (λ/2) -long air gap was introduced between the DP and CP1 layers. A radiation thermometer detected a temperature increase of 75.5 K in CP2 under 500 W microwave irradiation for 10 s, which was higher than the 43 K increase observed without the air gap. This demonstrates that the λ/2-air gap effectively provides thermal isolation between the DP and CP1 layers.

In this study, we present a method for filling molten solder into through-glass via (TGV) substrates using a pulse width modulated (PWM) vacuum suction system. The TGV substrates were fabricated using micro-electro-mechanical systems (MEMS) techniques, incorporating anodic bonding and glass reflow processes. The vacuum suction system comprises a vacuum chuck, pressure sensor, pulse control circuit, and solenoid valve. The solenoid valve modulates the vacuum level of the chuck by opening and closing. The switching frequency was set to 1 Hz with a 20% duty cycle. TGVs were fabricated in the glass substrates with diameters of 150 μm and thicknesses of 350 μm. The vacuum filling yield was approximately 30% at 40 kPa and exceeded 98% at 80 kPa vacuum level. X-ray imaging confirmed void-free filling results. The individual via resistance of the tin-filled TGVs was measured at 69.8 ± 38.5 mΩ using the four-probe method.

In zoom analog-to-digital converters (ADCs), due to the dynamic updating and scaling of fine reference voltages by coarse SAR ADC, traditional noise coupling technique cannot be directly applied to fine ΔΣ modulator, which may lead to modulator overload and a sharp decline in the signal-to-noise distortion ratio (SNDR). To address this issue, this article proposes a noise-coupled technique specifically designed for zoom ADCs. It establishes a mathematical model and determines the appropriate feedback voltage based on coarse quantization and the over-ranging factor, ultimately enhancing SNDR and energy efficiency. The zoom ADC is designed using a 180nm CMOS process and incorporates two integrators to achieve 3^rd-order noise-shaping capability (60 dB/dec). It achieves an SNDR of 105.7 dB at a sampling frequency of 256 kHz and an oversampling rate of 128, with a power consumption of only 90.25 μW. The SNDR-based Schreier figure-of-merit (FoMs) is 176.1 dB, indicating competitive performance in terms of high resolution and energy efficiency.

Analog computing-in-memory (ACIM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, inefficient analog-to-digital converters (ADC) will inhibit the performance improvement of this system. The primary contribution is in two aspects. First, we present a weight-flip-store coding technology that reduces the ADC resolution by one bit while maintaining the inference accuracy. Second, we propose a readout mechanism that can adaptively choose to skip high three-bit quantization cycles depending on input sparsity, further reducing ADC power. The experimental results show that the ADC power can be reduced by 28.5%-44.4%.

A low-power, fast-response transmitter based on frequency-shift keying (FSK) is presented and used in the Sub-GHz band. This transmitter uses the closed-loop modulation structure of a phase-locked loop (PLL) and maintains the constant loop bandwidth of a PLL to ensure a consistent data rate at each frequency point of Sub-GHz. A fast and accurate VCO frequency sub-band selection technology is proposed to reduce the selection time of the optimal variable capacitor array control bits of VCO, thus improving the response speed of PLL and transmitter. This transmitter is implemented in the SMIC 0.18 μm CMOS process. The measured results showed that the selection time of the optimal VCO frequency sub-band is only 3.04 us, and the Error Vector Magnitude (EVM) of the whole transmitter is 4.17% at 115 kHz data rate, meeting the wireless transmission requirements of the nodes of Internet of things.

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 μs, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.

This paper presents a highly integrated, relatively high data rate wake-up receiver (WuRX) designed and implemented in 65nm CMOS technology. The receiver operates at 2.4 GHz band and exhibits robustness against power supply variations, and achieves a data rate of 20kbps. It employs a sub-threshold enhanced differential structure for the envelope detector to enhance noise performance and a bias-free baseband amplifier to improve the sensitivity. Operating at a nominal voltage of 0.5V, the WuRX consumes just 98nW and achieves a sensitivity of -62.8dBm.

This article presents a novel low dropout regulator with high PSR and reliable stability. In order to achieve high PSR, this design use PSR enhance circuit to filter the voltage ripple from reference at low frequency, and achieving -82dB PSR at 1KHz with the load of 20mA. Besides, owing to the dynamic RC compensation network, this design can reconfigure the compensation resistor and capacitor, and achieve good stability at full load up to 250mA. Finally, this design was implemented with the 0.5-m CMOS technology, and the total quiescent current of the proposed LDO is only 12A.

This paper presents a SerDes receiver for medium-reach interconnection in a 28-nm CMOS process. It employs a CTLE and an adaptive quarter-rate loop-unrolling 5-tap DFE utilizing an SS-LMS algorithm to enable adaptive adjustment of tap coefficients under different channels. The proposed DFE contains CML-based summer with CMFB technology and two-stage dynamic comparator with an offset calibration loop. Simulation results show that this receiver can operate at 25 Gb/s data rate with a power efficiency of 5.99 pJ/bit, Its BER is less than 1E-12 and eye-wide-opening is 0.67 UI under 20.6-dB channel loss at 12.5 GHz Nyquist frequency.

To improve the performance of the boost circuit, a fuzzy inference systems (FIS) design method based on adaptive neural networks (ANN) system identification is proposed for the boost circuit. Using ANN for system identification based on training data to generate initial first-order Takagi—Sugeno (T-S) FIS. Adjust the FIS parameters by comparing them with the testing and checking data, and iterate until the error is within an acceptable range to form the final FIS. The steady-state and dynamic capabilities of the boost circuit under FIS control have been verified through simulation and experiments to be superior to traditional proportion integral differential (PID) control. The experimental results show that when the input voltage jumps from 28V to 22V, the boost speed of the boost circuit based on FIS control is improved by 21.5% compared to PID.

In this paper, we propose a novel MIMO-enabled integrated sensing and backscatter communication (MIMO-ISABC) system to serve multiple users, and focus on the transmit beamforming design for the system. Under the total transmit power constraint, we aim to design sensing and communication beams that meet both tag detection and communication requirements. First, we use minimum mean square error (MMSE) beamforming to design the beamforming vectors, followed by convex optimization to allocate power between sensing and communication. Then, we investigate a joint beamforming optimization problem to minimize the total transmit power while meeting the tag detection and communication requirements. To solve this, we transform the non-convex constraints into convex second-order cone constraints. The experimental results demonstrate the validity and performance of the proposed scheme and associated algorithms. The proposed MIMO-ISABC system offers great potential for applications in IoT scenarios.

Junction temperature calibration of power devices is important for estimating the junction temperature. In this paper, a pulse-current calibration method is proposed as a means of improving the efficiency of temperature calibration, utilizing the on-state voltage of SiC MOSFET as a calibration parameter. Firstly, the junction temperature calibration platform is constructed and a suitable parameter acquisition system is implemented. Subsequently, the corresponding calibration strategy and experimental flow are proposed, and the calculation of bus capacitance and inductance is given. Ultimately, the self-heating of the SiC MOSFET during the calibration is evaluated quantificationally. The results demonstrate that the self-heating effects associated with the proposed calibration method are negligible, thereby confirming the feasibility of the proposed strategy. Furthermore, the method is capable of acquiring a substantial amount of data in a single experimental test, which markedly enhances the efficiency of the calibration process.

There are a large number of 2.45G weak energy signals in the environment, which can be collected and realized for applications by microwave wireless energy transfer systems (WMPT). However, the rectification efficiency of WMPT with Si MOSFET as the core rectifier component is low at 2.45G weak energy density. In this paper, a high carrier mobility composite strain GeOI material is proposed and designed, and the optimal crystal orientation/crystal plane of the composite strain GeOI PMOSFET channel is optimized and determined by quantum mechanics related theory. The GeOI PMOSFET device is simulated and designed using Silvaco software, while a half-wave rectifier circuit with a load of 0.5pf and 30kΩ is built in the Mixed-mode module, and its peak rectification efficiency can reach 42.1% at 3.89dBm. The rectification efficiency at -12.1dBm 2.45G weak energy density reaches 6.5%, which is 3.96 times higher than that of the equivalent body Si MOSFET.