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Created June 29, 2024 05:05
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verilator sim sample main
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main.cpp
#include "Vsoc_slideshow.h"
////#include "VBriey_Axi4VgaCtrl.h"
////#include "VBriey_VgaCtrl.h"
//#ifdef REF
//#include "VBriey_RiscvCore.h"
//#endif
#include "verilated.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <stdint.h>
#include <cstring>
#include <string.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <iomanip>
#include <time.h>
#include <unistd.h>
#include "Vsoc_slideshow_VexRiscvAxi4.h"
#include "./common/framework.h"
#include "./common/jtag.h"
#include "./common/uart.h"
class VexRiscvTracer : public SimElement{
public:
Vsoc_slideshow_VexRiscvAxi4 *cpu;
ofstream instructionTraces;
ofstream regTraces;
VexRiscvTracer(Vsoc_slideshow_VexRiscvAxi4 *cpu){
this->cpu = cpu;
#ifdef TRACE_INSTRUCTION
instructionTraces.open ("instructionTrace.log");
#endif
#ifdef TRACE_REG
regTraces.open ("regTraces.log");
#endif
}
virtual void preCycle(){
#ifdef TRACE_INSTRUCTION
if(cpu->writeBack_arbitration_isFiring){
instructionTraces << hex << setw(8) << cpu->writeBack_INSTRUCTION << endl;
}
#endif
#ifdef TRACE_REG
if(cpu->writeBack_RegFilePlugin_regFileWrite_valid == 1 && cpu->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
regTraces << " PC " << hex << setw(8) << cpu->writeBack_PC << " : reg[" << dec << setw(2) << (uint32_t)cpu->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << hex << setw(8) << cpu->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
}
#endif
}
};
#include <SDL2/SDL.h>
#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
class BrieyWorkspace : public Workspace<Vsoc_slideshow>{
public:
BrieyWorkspace() : Workspace("Briey"){
//ClockDomain *axiClk = new ClockDomain(&top->io_mainClk,NULL,20000,100000);
// ( ,reset, period, delay)
ClockDomain *axiClk = new ClockDomain(&top->io_mainClk,NULL,12000,100000); // 83MHz
//ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000);
AsyncResetx *asyncResetx = new AsyncResetx(&top->io_asyncResetx,50000*1);
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,80000);
UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200);
timeProcesses.push_back(axiClk);
//timeProcesses.push_back(vgaClk);
timeProcesses.push_back(asyncResetx);
timeProcesses.push_back(jtag);
timeProcesses.push_back(uartRx);
top->io_uart_rxd = 1;
#ifdef TRACE
//speedFactor = 100e-6;
//cout << "Simulation caped to " << timeToSec << " of real time"<< endl;
#endif
//axiClk->add(new VexRiscvTracer(top->Briey->axi_core_cpu));
//#ifdef VGA
//Vga *vga = new Vga(top,640,480);
//vgaClk->add(vga);
//#endif
//top->io_coreInterrupt = 0;
}
/*bool trigged = false;
uint32_t frameStartCounter = 0;
virtual void dump(uint64_t i){
if(!trigged) {
if(top->Briey->axi_vgaCtrl->vga_ctrl->io_frameStart) {
frameStartCounter++;
if(frameStartCounter < 3*32) cout << "**\n" << endl;
}
if(top->Briey->axi_vgaCtrl->vga_ctrl->io_error && frameStartCounter > 3*32) trigged = true;
}
if(trigged)Workspace::dump(i);
}*/
};
struct timespec timer_start(){
struct timespec start_time;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time);
return start_time;
}
long timer_end(struct timespec start_time){
struct timespec end_time;
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &end_time);
uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - start_time.tv_sec*1e9 - start_time.tv_nsec;
return diffInNanos;
}
int main(int argc, char **argv, char **env) {
Verilated::randReset(2);
Verilated::commandArgs(argc, argv);
printf("BOOT\n");
timespec startedAt = timer_start();
BrieyWorkspace().run(1e9);
uint64_t duration = timer_end(startedAt);
cout << endl << "****************************************************************" << endl;
exit(0);
}
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