[2311.03841] Preliminary Design of Scalable Hardware Integrated Platform for LLRF Application
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Computer Science > Hardware Architecture

arXiv:2311.03841 (cs)
[Submitted on 7 Nov 2023]

Title:Preliminary Design of Scalable Hardware Integrated Platform for LLRF Application

Authors:Lin Jiang, Jingjun Wen, Tao Xue, Xiaowei Guo, Haoyan Yang, Qiutong Pan, Jianmin Li, Yinong Liu, Liangjun Wei
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Abstract:In this paper, the SHIP4LLRF (Scalable Hardware Integrated Platform for LLRF) based on 6U VPX-standard was designed preliminarily, which includes 6U mother board and two HPC FPGA mezzanine cards (FMCs). The ADC and DAC FMC is based on ADS54J60 from TI and LTC2000Y-16 form ADI, respectively. The system mother board is based on Xilinx Kintex UltraScale KU060, which also features 64-bit DDR4 SDRAM, QSFP and USB3.0 interfaces. Each FMC connector is assigned 58 pairs of LVDS standard IOs and 8 pairs of GTH high-speed serial lanes. Besides, the mother board is equipped with the self-developed ZYNQBee2 module based on ZYNQ7010 for slow control such as EPICS. All ADC or DAC raw data in each SHIP4LLEF is compressed loss-less without triggering and transmitted to the process board. A scalar quantization method which is in development is used for lossless compression of ADC raw data, the process board will decompress the ADC data and perform a digital algorithm to measure the amplitude and phase of the high frequency signal. This de-sign is scalable for testing and upgradability, mean-while, the trigger-less data transmission enable this system participate in both local (rack-scale) and accelerator-wide communication networks.
Comments: Talk presented at LLRF Workshop 2023 (LLRF2023, arXiv: 2310.03199)
Subjects: Hardware Architecture (cs.AR); Accelerator Physics (physics.acc-ph)
Report number: LLRF2023/38
Cite as: arXiv:2311.03841 [cs.AR]
  (or arXiv:2311.03841v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2311.03841

Submission history

From: Lin Jiang [view email]
[v1] Tue, 7 Nov 2023 09:44:46 UTC (767 KB)
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