Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers

Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers

Authors Muhammad Ali Awan , Pedro F. Souto , Konstantinos Bletsas , Benny Akesson , Eduardo Tovar



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Author Details

Muhammad Ali Awan
  • CISTER Research Centre and ISEP, Porto, Portugal
Pedro F. Souto
  • University of Porto, Faculty of Engineering and CISTER Research Centre, Porto, Portugal
Konstantinos Bletsas
  • CISTER Research Centre and ISEP, Porto, Portugal
Benny Akesson
  • Embedded Systems Innovation, Eindhoven, the Netherlands
Eduardo Tovar
  • CISTER Research Centre and ISEP, Porto, Portugal

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Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, and Eduardo Tovar. Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Leibniz International Proceedings in Informatics (LIPIcs), Volume 106, pp. 2:1-2:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018) https://doi.org/10.4230/LIPIcs.ECRTS.2018.2

Abstract

In multicore architectures, there is potential for contention between cores when accessing shared resources, such as system memory. Such contention scenarios are challenging to accurately analyse, from a worst-case timing perspective. One way of making memory contention in multicores more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the number of accesses performed by any given core over time by using periodically replenished per-core budgets. Typically, this assumes that all cores access memory via a single shared memory controller. However, ever-increasing bandwidth requirements have brought about architectures with multiple memory controllers. These control accesses to different memory regions and are potentially shared among all cores. While this presents an opportunity to satisfy bandwidth requirements, existing analysis designed for a single memory controller are no longer safe. 
This work formulates a worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. This stall analysis can be integrated into the schedulability analysis of systems under fixed-priority partitioned scheduling. Five heuristics for assigning tasks and memory budgets to cores in a stall-cognisant manner are also proposed. We experimentally quantify the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers, and also evaluate the five heuristics for different system characteristics.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Real-time operating systems
  • Computer systems organization → Real-time system architecture
Keywords
  • multiple memory controllers
  • memory regulation
  • multicore

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