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A New Fault Tolerant Routing Algorithm for Networks on Chip

A New Fault Tolerant Routing Algorithm for Networks on Chip

Chakib Nehnouh, Mohamed Senouci
Copyright: © 2019 |Volume: 10 |Issue: 3 |Pages: 18
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781522571988|DOI: 10.4018/IJERTCS.2019070105
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MLA

Nehnouh, Chakib, and Mohamed Senouci. "A New Fault Tolerant Routing Algorithm for Networks on Chip." IJERTCS vol.10, no.3 2019: pp.68-85. https://doi.org/10.4018/IJERTCS.2019070105

APA

Nehnouh, C. & Senouci, M. (2019). A New Fault Tolerant Routing Algorithm for Networks on Chip. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 10(3), 68-85. https://doi.org/10.4018/IJERTCS.2019070105

Chicago

Nehnouh, Chakib, and Mohamed Senouci. "A New Fault Tolerant Routing Algorithm for Networks on Chip," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 10, no.3: 68-85. https://doi.org/10.4018/IJERTCS.2019070105

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Abstract

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones.

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