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Medical Image Encryption: Microcontroller and FPGA Perspective

Medical Image Encryption: Microcontroller and FPGA Perspective

Sundararaman Rajagopalan, Siva Janakiraman, Amirtharajan Rengarajan
Copyright: © 2019 |Pages: 27
ISBN13: 9781522579526|ISBN10: 1522579524|EISBN13: 9781522579533
DOI: 10.4018/978-1-5225-7952-6.ch014
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MLA

Rajagopalan, Sundararaman, et al. "Medical Image Encryption: Microcontroller and FPGA Perspective." Medical Data Security for Bioengineers, edited by Butta Singh, et al., IGI Global, 2019, pp. 278-304. https://doi.org/10.4018/978-1-5225-7952-6.ch014

APA

Rajagopalan, S., Janakiraman, S., & Rengarajan, A. (2019). Medical Image Encryption: Microcontroller and FPGA Perspective. In B. Singh, B. Saini, D. Singh, & A. Pandey (Eds.), Medical Data Security for Bioengineers (pp. 278-304). IGI Global Scientific Publishing. https://doi.org/10.4018/978-1-5225-7952-6.ch014

Chicago

Rajagopalan, Sundararaman, Siva Janakiraman, and Amirtharajan Rengarajan. "Medical Image Encryption: Microcontroller and FPGA Perspective." In Medical Data Security for Bioengineers, edited by Butta Singh, et al., 278-304. Hershey, PA: IGI Global, 2019. https://doi.org/10.4018/978-1-5225-7952-6.ch014

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Abstract

The healthcare industry has been facing a lot of challenges in securing electronic health records (EHR). Medical images have found a noteworthy position for diagnosis leading to therapeutic requirements. Millions of medical images of various modalities are generally safeguarded through software-based encryption. DICOM format is a widely used medical image type. In this chapter, DICOM image encryption implemented on cyclone FPGA and ARM microcontroller platforms is discussed. The methodology includes logistic map, DNA coding, and LFSR towards a balanced confusion – diffusion processes for encrypting 8-bit depth 256 × 256 resolution of DICOM images. For FPGA realization of this algorithm, the concurrency feature has been utilized by simultaneous processing of 128 × 128 pixel blocks which yielded a throughput of 79.4375 Mbps. Noticeably, the ARM controller which replicated this approach through sequential embedded “C” code took 1248 bytes in flash code memory and Cyclone IV FPGA consumed 21,870 logic elements for implementing the proposed encryption scheme with 50 MHz operating clock.

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